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| motorola.com/semiconductors m68hc08 microcontrollers mc68HC908BD48 data sheet mc68HC908BD48/d rev. 2 9/2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola 3 mc68HC908BD48 data sheet to provide the most up-to-date info rmation, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to veri fy you have the latest information available, refer to: http://motorola.com/semiconductors/ the following revision history table summarizes cha nges contained in this document. for your conven ience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. this product incorporates superflash? technol ogy licensed from sst. ? motorola, inc., 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . revision history data sheet mc68HC908BD48 ? rev. 2.0 4 motorola revision history date revision level description page number(s) 9/2003 2 incorporated addendum to rev. 1.0 data sheet. removed 28-pin pdip references. section 10. timer interface module (tim) ? timer discrepancies corrected throughout this section. 125 section 22. mechanical specifications ? replaced incorrect 44-pin qfp drawing, case 824e to case 824a. 283 section 9. monitor rom (mon) ? updated figure 9-1 . monitor mode circuit . 117 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola list of sections 5 data sheet ? mc68HC908BD48 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 25 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 35 section 3. random-a ccess memory (ram) . . . . . . . . . . 53 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . 55 section 5. configuration register (config) . . . . . . . . . 63 section 6. central processor unit (cpu) . . . . . . . . . . . . 67 section 7. system integration mo dule (sim) . . . . . . . . . 87 section 8. oscillator (osc ) . . . . . . . . . . . . . . . . . . . . . . 111 section 9. monitor rom (mon) . . . . . . . . . . . . . . . . . . . 115 section 10. timer interface module (tim) . . . . . . . . . . . 125 section 11. pulse width modulato r (pwm) . . . . . . . . . . 147 section 12. analog-to-digital converter (adc) . . . . . . 153 section 13. universal serial bu s module (usb) . . . . . . 163 section 14. multi-master iic in terface (mmiic) . . . . . . . 179 section 15. ddc12ab interface . . . . . . . . . . . . . . . . . . . 193 section 16. sync processo r . . . . . . . . . . . . . . . . . . . . . . 209 section 17. input/output (i/o) port s . . . . . . . . . . . . . . . 229 section 18. external interrupt (irq ) . . . . . . . . . . . . . . . 251 section 19. computer operatin g properly (cop) . . . . 257 section 20. break module (brk) . . . . . . . . . . . . . . . . . . 263 section 21. electrical sp ecifications. . . . . . . . . . . . . . . 271 section 22. mechanical specificati ons . . . . . . . . . . . . . 283 section 23. ordering in formation . . . . . . . . . . . . . . . . . 285 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections data sheet mc68HC908BD48 ? rev. 2.0 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola table of contents 7 data sheet ? mc68HC908BD48 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 35 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC908BD48 ? rev. 2.0 8 table of contents motorola 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.4 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 56 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 61 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.3.1 configuration register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.3.2 configuration register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .65 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 75 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908BD48 ? rev. 2.0 data sheet motorola table of contents 9 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 section 7. system integration module (sim) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 91 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 91 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 93 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 95 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 96 7.5.2 sim counter during stop mode reco very . . . . . . . . . . . . . . 97 7.5.3 sim counter and reset st ates. . . . . . . . . . . . . . . . . . . . . . . 97 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 104 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC908BD48 ? rev. 2.0 10 table of contents motorola 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 108 7.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 109 7.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 110 section 8. oscillator (osc) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.3 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . .112 8.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 113 8.4.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 113 8.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 113 8.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . 113 8.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . 114 section 9. monitor rom (mon) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908BD48 ? rev. 2.0 data sheet motorola table of contents 11 section 10. timer interface module (tim) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 130 10.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .131 10.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 131 10.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 132 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 133 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 10.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 137 10.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 139 10.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 140 10.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 141 10.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 145 section 11. pulse width modulator (pwm) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.4 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC908BD48 ? rev. 2.0 12 table of contents motorola 11.4.1 pwm data registers 0 to 15 (0pwm?15pwm). . . . . . . . . 150 11.4.2 pwm control registers 1 and 2 (pwmcr1:pwmcr2) . . 151 section 12. analog-to-dig ital converter (adc) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 12.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 12.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 12.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 12.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 12.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.7.1 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .158 12.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 161 section 13. universal se rial bus module (usb) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.5 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 13.5.1 usb address register (uadr) . . . . . . . . . . . . . . . . . . . . . 166 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908BD48 ? rev. 2.0 data sheet motorola table of contents 13 13.5.2 usb interrupt register (uintr). . . . . . . . . . . . . . . . . . . . . 166 13.5.3 usb interrupt register 1 (uir1). . . . . . . . . . . . . . . . . . . . . 169 13.5.4 usb control register 0 (ucr0). . . . . . . . . . . . . . . . . . . . . 171 13.5.5 usb control register 1 (ucr1). . . . . . . . . . . . . . . . . . . . . 172 13.5.6 usb control register 2 (ucr2). . . . . . . . . . . . . . . . . . . . . 174 13.5.7 usb status register (usr) . . . . . . . . . . . . . . . . . . . . . . . . 175 13.5.8 usb endpoint 0 da ta registers 0 to 7 (ud0r0?ud0r7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.5.9 usb endpoint 1/2 da ta registers 0 to 7 (ud1r0?ud1r7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 section 14. multi-master iic interface (mmiic) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.5 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 14.5.1 multi-master iic address regist er (mmadr) . . . . . . . . . . 182 14.5.2 multi-master iic control register (mmcr) . . . . . . . . . . . . 183 14.5.3 multi-master iic ma ster control register (mimcr) . . . . . . 184 14.5.4 multi-master iic stat us register (mmsr) . . . . . . . . . . . . . 186 14.5.5 multi-master iic data transm it register (mmdtr) . . . . . . 188 14.5.6 multi-master iic data receiv e register (mmdrr ) . . . . . . 189 14.6 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 190 section 15. ddc12ab interface 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.5 ddc protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.6 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC908BD48 ? rev. 2.0 14 table of contents motorola 15.6.1 ddc address register (dadr) . . . . . . . . . . . . . . . . . . . . . 196 15.6.2 ddc2 address register (d2adr) . . . . . . . . . . . . . . . . . . . 197 15.6.3 ddc control register (dcr) . . . . . . . . . . . . . . . . . . . . . . . 198 15.6.4 ddc master control register (d mcr) . . . . . . . . . . . . . . . 199 15.6.5 ddc status register (dsr) . . . . . . . . . . . . . . . . . . . . . . . . 202 15.6.6 ddc data transmit r egister (ddtr) . . . . . . . . . . . . . . . . 204 15.6.7 ddc data receive register (ddrr) . . . . . . . . . . . . . . . . . 205 15.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 206 section 16. sync processor 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.5.1 polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.1.1 hsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.1.2 vsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.1.3 composite sync polarity detect ion . . . . . . . . . . . . . . . . 214 16.5.2 sync signal counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.5.3 polarity controll ed hsynco and vsynco outputs. . . . . 215 16.5.4 clamp pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.5 low vertical frequency detect . . . . . . . . . . . . . . . . . . . . . 217 16.6 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 16.6.1 sync processor control & stat us register ( spcsr). . . . . 217 16.6.2 sync processor input/output control register (spiocr) . 219 16.6.3 vertical frequency registers (vfrs) . . . . . . . . . . . . . . . . . 221 16.6.4 hsync frequency registers (hfrs). . . . . . . . . . . . . . . . . . 223 16.6.5 sync processor control register 1 (spcr1). . . . . . . . . . . 225 16.6.6 h&v sync output control regi ster (hvocr) . . . . . . . . . . 226 16.7 system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908BD48 ? rev. 2.0 data sheet motorola table of contents 15 section 17. input/output (i/o) ports 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 234 17.3.3 port a options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 237 17.4.3 port b options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.5.3 port c options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.6.3 port d options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.7.3 port e options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 section 18. external interrupt (irq) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 18.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 255 18.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 255 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC908BD48 ? rev. 2.0 16 table of contents motorola section 19. computer op erating properly (cop) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 19.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 19.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 19.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 260 19.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 19.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 19.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 19.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 19.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 262 section 20. break module (brk) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 20.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 266 20.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .266 20.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 266 20.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 266 20.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC908BD48 ? rev. 2.0 data sheet motorola table of contents 17 20.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 20.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 20.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 267 20.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 270 section 21. electrical specifications 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 21.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 272 21.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 273 21.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 21.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 274 21.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.9 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 21.10 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 277 21.11 usb low speed source electrical characterist ics. . . . . . . . . 278 21.12 timer interface module characteristics . . . . . . . . . . . . . . . . . 278 21.13 ddc12ab/mmiic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 21.13.1 ddc12ab/mmiic interface input signal timing . . . . . . . . 279 21.13.2 ddc12ab/mmiic interface output signal timing . . . . . . . 279 21.14 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 21.15 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC908BD48 ? rev. 2.0 18 table of contents motorola section 22. mechanic al specifications 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22.4 42-pin shrink dual in -line package (sdip) . . . . . . . . . . . . . . 283 22.5 44-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 284 section 23. ordering information 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 23.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola list of figures 19 data sheet ? mc68HC908BD48 list of figures figure title page 1-1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1-2 44-pin qfp pin assi gnments . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1-3 42-pin sdip pin a ssignments . . . . . . . . . . . . . . . . . . . . . . . . . 30 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .39 4-1 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 56 4-2 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 60 4-3 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 61 4-4 flash block protec t start address . . . . . . . . . . . . . . . . . . . . .62 5-1 configuration register 0 (config0) . . . . . . . . . . . . . . . . . . . . 64 5-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . . 65 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 72 7-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7-2 osc clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-3 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7-4 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-5 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7-6 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7-7 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7-8 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7-9 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7-10 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures data sheet mc68HC908BD48 ? rev. 2.0 20 list of figures motorola figure title page 7-11 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . 103 7-12 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . . 103 7-13 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7-14 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . 106 7-15 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 106 7-16 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7-17 stop mode recovery fr om interrupt or break . . . . . . . . . . . . . 107 7-18 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 108 7-19 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 109 7-20 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 110 8-1 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . .112 9-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9-2 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 9-5 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 10-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10-2 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 132 10-3 tim status and control register (tsc ) . . . . . . . . . . . . . . . . . 137 10-4 tim counter register s (tcnth:tcntl) . . . . . . . . . . . . . . . . 140 10-5 tim counter modulo registers (tmodh:tmodl) . . . . . . . . . 141 10-6 tim channel status and contro l registers (tsc0:tsc1) . . . 142 10-7 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 10-8 tim channel registers (tch0h/l:t ch1h/l). . . . . . . . . . . . . 146 11-1 pwm data registers 0 to 15 (0 pwm?15pwm) . . . . . . . . . . . 150 11-2 pwm control register 1 and 2 (pwmcr1:pwmcr2). . . . . . 151 11-3 8-bit pwm output waveforms . . . . . . . . . . . . . . . . . . . . . . . . 152 12-1 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12-2 adc status and control register (adscr) . . . . . . . . . . . . . . 158 12-3 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12-4 adc input clock register (adiclk) . . . . . . . . . . . . . . . . . . . 161 13-1 usb address register ( uadr) . . . . . . . . . . . . . . . . . . . . . . .166 13-2 usb interrupt register (uintr) . . . . . . . . . . . . . . . . . . . . . . . 166 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mc68HC908BD48 ? rev. 2.0 data sheet motorola list of figures 21 figure title page 13-3 usb interrupt register 1 (uir1) . . . . . . . . . . . . . . . . . . . . . . . 169 13-4 usb control register 0 (ucr0) . . . . . . . . . . . . . . . . . . . . . . . 171 13-5 usb control register 1 (ucr1) . . . . . . . . . . . . . . . . . . . . . . . 172 13-6 usb control register 2 (ucr2) . . . . . . . . . . . . . . . . . . . . . . . 174 13-7 usb status register (usr ) . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13-8 usb endpoint 0 data register s 0 to 7 (ud0r0?ud0r7) . . . 177 13-9 usb endpoint 1 data register s 0 to 7 (ud1r0?ud1r7) . . . 177 14-1 multi-master iic address register (mmadr). . . . . . . . . . . . . 182 14-2 multi-master iic control register (mmcr). . . . . . . . . . . . . . . 183 14-3 multi-master iic master control register (mimcr) . . . . . . . . 184 14-4 multi-master iic status register (mmsr) . . . . . . . . . . . . . . . 186 14-5 multi-master iic data transmit register (mmdtr) . . . . . . . . 188 14-6 multi-master iic data receive r egister (mmdrr) . . . . . . . . 189 14-7 data transfer sequenc es for master/slave transmit/receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15-1 ddc address register ( dadr) . . . . . . . . . . . . . . . . . . . . . . .196 15-2 ddc2 address register (d2adr) . . . . . . . . . . . . . . . . . . . . . 197 15-3 ddc control register ( dcr) . . . . . . . . . . . . . . . . . . . . . . . . . 198 15-4 ddc master control r egister (dmcr). . . . . . . . . . . . . . . . . . 199 15-5 ddc status register (dsr ) . . . . . . . . . . . . . . . . . . . . . . . . . . 202 15-6 ddc data transmit register (ddtr). . . . . . . . . . . . . . . . . . . 204 15-7 ddc data receive regi ster (ddrr) . . . . . . . . . . . . . . . . . . . 205 15-8 data transfer sequenc es for master/slave transmit/receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16-1 sync processor block diagram . . . . . . . . . . . . . . . . . . . . . . .213 16-2 clamp pulse output timing . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16-3 sync processor control & status register (spcsr) . . . . . . . 217 16-4 sync processor input/output cont rol register (spiocr) . . . 219 16-5 vertical frequency high register . . . . . . . . . . . . . . . . . . . . . . 221 16-6 vertical frequency low register . . . . . . . . . . . . . . . . . . . . . . 221 16-7 hsync frequency high regist er . . . . . . . . . . . . . . . . . . . . . . . 223 16-8 hsync frequency low regist er . . . . . . . . . . . . . . . . . . . . . . .223 16-9 sync processor control register 1 (spcr1) . . . . . . . . . . . . . 225 16-10 h&v sync output control register (hvocr) . . . . . . . . . . . . 226 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures data sheet mc68HC908BD48 ? rev. 2.0 22 list of figures motorola figure title page 17-1 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17-2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 234 17-3 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 17-4 pwm control register 1 (pwmcr1) . . . . . . . . . . . . . . . . . . . 235 17-5 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 237 17-7 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 17-8 pwm control register 1 (pwmcr1) . . . . . . . . . . . . . . . . . . . 238 17-9 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17-10 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 240 17-11 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17-12 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17-13 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 243 17-14 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17-15 port d configuration r egister (pdcr) . . . . . . . . . . . . . . . . . . 245 17-16 port e data register (pte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17-17 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 248 17-18 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17-19 configuration register 0 (config0) . . . . . . . . . . . . . . . . . . . 250 18-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18-2 irq status and contro l register (intscr) . . . . . . . . . . . . . . 256 19-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 19-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . 260 19-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 261 20-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 265 20-2 break status and control register (brkscr). . . . . . . . . . . . 267 20-3 break address register high (brkh) . . . . . . . . . . . . . . . . . . 268 20-4 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 268 20-5 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 269 20-6 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 270 21-1 adc input voltage vs. step readings . . . . . . . . . . . . . . . . . . 277 22-2 42-pin sdip (case #858) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22-3 44-pin qfp (case #824a) . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola list of tables 23 data sheet ? mc68HC908BD48 list of tables table title page 1-1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7-1 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .90 7-2 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7-3 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7-4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7-5 sim registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9-3 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 121 9-4 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 122 9-5 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 122 9-6 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 123 9-7 readsp (read stack po inter) command . . . . . . . . . . . . . . . 123 9-8 run (run user program) command . . . . . . . . . . . . . . . . . . . 124 9-9 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 124 10-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .128 10-3 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10-4 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 144 11-1 pwm i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 148 11-2 pwm channels and port i/o pins. . . . . . . . . . . . . . . . . . . . . . 151 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables data sheet mc68HC908BD48 ? rev. 2.0 24 list of tables motorola table title page 12-1 adc register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12-2 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12-3 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 13-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13-2 usb i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14-2 mmiic i/o register summa ry. . . . . . . . . . . . . . . . . . . . . . . . . 181 14-3 baud rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15-2 ddc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15-3 baud rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16-2 sync processor i/o register summar y . . . . . . . . . . . . . . . . . 212 16-3 sync output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16-4 sync output polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16-5 atpol, vinvo, and hinvo setting. . . . . . . . . . . . . . . . . . . .219 16-6 sample vertical frame frequencies . . . . . . . . . . . . . . . . . . . 222 16-7 clamp pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16-8 hsync polarity detect ion pulse width . . . . . . . . . . . . . . . . . 225 16-9 atpol, vinvo, and hinvo setting. . . . . . . . . . . . . . . . . . . .226 16-10 free-running h sync and vsync options . . . . . . . . . . . . . 227 17-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .230 17-2 port control register bits summary. . . . . . . . . . . . . . . . . . . .232 17-3 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17-4 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17-5 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17-6 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17-7 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 18-1 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .253 20-1 break module i/o register summary . . . . . . . . . . . . . . . . . . . 265 23-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola general description 25 data sheet ? mc68HC908BD48 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.2 introduction the mc68HC908BD48 is a me mber of the low-co st, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. with special modules such as t he sync processor, analog-to-digital converter, pulse modulator module, ddc12ab interface, multi-master iic interface, and universal serial bus interface, the mc68HC908BD48 is designed specifical ly for use in digi tal monitor systems. 1.3 features features of the mc 68HC908BD48 mcu incl ude the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC908BD48 ? rev. 2.0 26 general description motorola low-power design; fully st atic with stop and wait modes 5v operating voltage 6mhz internal bus frequency; with 24mhz external crystal 48,128 bytes of on -chip flash memory 1,024 bytes of on-chip r andom access memory (ram) sync signal processor with the following features: ? horizontal and vertic al frequency counters ? low vertical frequency indicator (40.7hz) ? polarity controlled hsync and vsync outputs from separate sync or composite sync inputs ? internal generated free-running hsyn c and vsync pulses ? clamp pulse output to the external pre-amp chip 6-channel, 8-bit analog-to-d igital converter (adc) 16-channel, 8-bit pulse width modulator (pwm) full universal serial bus (usb) specification 1. 0 compliant low- speed bus with 3 endpoints: ? 1 control endpoint (two 8-byte buffer) ? 2 interrupt endpoints ( one 8-byte buffer shared) on-chip 3.3v regulator for usb pull-up resistor ddc12ab 1 module with the following: ? ddc1 hardware ? multi-master iic 2 hardware for ddc2ab; with dual address additional multi- master iic module 16-bit, 2-channel timer interfac e modules (tim) with selectable input capture, output com pare, and pwm capability on one channel 32 general purpose input/out put (i/o) pins, including: ? 4 open-drain pins 1. ddc is a vesa bus standard. 2. iic is a proprietary philips interface bus. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description mcu block diagram mc68HC908BD48 ? rev. 2.0 data sheet motorola general description 27 system protection features: ? optional computer operati ng properly (cop) reset ? illegal opcode detection with reset ? illegal address detection with reset flash memory security 1 master reset pin with intern al pull-up and power-on reset irq with programmable pull- up and schmitt-trigger input 42-pin sdip and 44-pin qfp packages features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68HC908BD48. 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC908BD48 ? rev. 2.0 28 general description motorola figure 1-1. mcu block diagram system integration module monitor module multi-master iic pulse width modulator module universal serial bus arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 80 bytes user flash ? 48,128 bytes user ram ? 1024 bytes monitor rom ? 512+470 bytes user flash vector space ? 26 bytes external irq module ddrd portd ddre porte internal bus ? osc1 ? osc2 rst irq interface module interface module 8-bit analog-to-digital converter module computer operating properly module ptd6/iicsda ? ptd5/iicscl ? ptd4/clamp ptd3/ddcscl ? ptd2/ddcsda ? ptd1/d? ? ptd0/d+ ? pte1/hsynco pte0/sog/tch0 2-channel timer interface module 2 ddc12ab interface module power-on reset module sync processor module power v ss v dd v ss1 v dd3 ? pin is +5v open-drain ? pin is +3.3v pte2/vsynco oscillator portb ddrb ptb7/pwm7?ptb0/pwm0 usb voltage regulator security module monitor mode entry module hsync vsync porta ddra pta7/pwm15?pta0/pwm8 portc ddrc ptc5/adc5?ptc0/adc0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68HC908BD48 ? rev. 2.0 data sheet motorola general description 29 1.5 pin assignments figure 1-2. 44-pin qfp pin assignments 44 34 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 12 23 osc2 ptc4/adc4 irq pte0/sog/tch0 osc1 vss rst ptb7/pwm7 ptb6/pwm6 ptb5/pwm5 ptc5/adc5 pta3/pwm11 pta5/pwm13 pta6/pwm14 pta7/pwm15 pta4/pwm12 pta2/pwm10 ptd5/iicscl ptd6/iicsda pta0/pwm8 ptd4/clamp pta1/pwm9 ptb0/pwm0 pte1/hsynco pte2/vsynco ptb4/pwm4 ptb3/pwm3 ptd3/ddcscl ptd2/ddcsda vss1 ptb2/pwm2 ptb1/pwm1 nc vdd3 vsync pd1/d? pd0/d+ nc ptc3/adc3 ptc2/adc2 ptc1/adc1 ptc0/adc0 hsync vdd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC908BD48 ? rev. 2.0 30 general description motorola figure 1-3. 42-pin sd ip pin assignments 21 22 pta2/pwm10 pta3/pwm11 ptd5/iicscl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 ptd6/iicsda pta0/pwm8 pta5/pwm13 pta6/pwm14 pta7/pwm15 osc2 ptc4/adc4 irq pte0/sog/tch0 ptb0/pwm0 pte1/hsynco pte2/vsynco ptc3/adc3 ptc2/adc2 ptc1/adc1 ptc0/adc0 hsync ptb4/pwm4 ptb3/pwm3 ptd3/ddcscl ptd2/ddcsda vss1 vdd3 vsync ptb2/pwm2 ptb1/pwm1 pd1/d? pd0/d+ vdd osc1 vss rst ptb7/pwm7 ptb6/pwm6 ptb5/pwm5 ptc5/adc5 ptd4/clamp 20 23 pta1/pwm9 pta4/pwm12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68HC908BD48 ? rev. 2.0 data sheet motorola general description 31 1.6 pin functions description of the pin f unctions are provided in table 1-1 . table 1-1. pin functions pin name pin description vdd power supply input to the mcu. vss power supply ground. vdd3 3.3v regulated output from the mcu. vss1 power supply ground. osc1 osc2 connections to the on-chip oscillator. an external clock can be connected directly to osc1; with osc2 floating. these are 3.3v pins. see section 8. oscillator (osc) . rst a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. this pin contains an internal pullup resistor. see section 7. system integration module (sim) . irq external irq pin; with software programmable internal pull-up and schmitt trigger input. this pin is also used for mode entry selection. see section 7. system integration module (sim) . vsync vsync input to the sync processor. see section 16. sync processor . hsync hsync input to the sync processor. see section 16. sync processor . pta7/pwm15?pta0/pwm8 these are shared-function pins. each pin can be configured as a standard i/o pin or a pwm output channel. see section 17. input/output (i/o) ports and section 11. pulse width modulator (pwm) . ptb7/pwm7?ptb0/pwm0 these are shared-function pins. each pin can be configured as a standard i/o pin or a pwm output channel. see section 17. input/output (i/o) ports and section 11. pulse width modulator (pwm) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC908BD48 ? rev. 2.0 32 general description motorola ptc5/adc5?ptc0/adc0 these are shared-function pins. each pin can be configured as a standard i/o pin or an adc input channel. see section 17. input/output (i/o) ports and section 12. analog-to- digital converter (adc) . ptd6/iicsda this is a shared function pin. it can be configured as a standard i/o pin or the data line of the multi- master iic module. this pin is open-drain when configured as output. see section 17. input/output (i/o) ports and section 14. multi-master iic interface (mmiic) . ptd5/iicscl this is a shared function pin. it can be configured as a standard i/o pin or the clock line of the multi- master iic module. this pin is open-drain when configured as output. see section 17. input/output (i/o) ports and section 14. multi-master iic interface (mmiic) . ptd4/clamp this is a shared function pin. it can be configured as a standard i/o pin or the clamp output from the sync processor. see section 17. input/output (i/o) ports and section 16. sync processor . ptd3/ddcscl this is a shared function pin. it can be configured as a standard i/o pin or as the clock line of the ddc12ab module. this pi n is open-drain when configured as output. see section 17. input/output (i/o) ports and section 15. ddc12ab interface . ptd2/ddcsda this is a shared function pin. it can be configured as a standard i/o pin or the data line of the ddc12ab module. this pi n is open-drain when configured as output. see section 17. input/output (i/o) ports and section 15. ddc12ab interface . ptd1/d? ptd0/d+ these are 3.3v, shared function pins. the pins can be configured as standard i/o pins or usb interface differential data lines. see section 17. input/output (i/o) ports and section 13. universal se rial bus module (usb) . table 1-1. pin functions pin name pin description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68HC908BD48 ? rev. 2.0 data sheet motorola general description 33 note: any unused inputs and i/o po rts should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68HC908BD48 do not require te rmination, termination is recommended to reduce the possi bility of static damage. pte2/vsynco this is a shared function pin. it can be configured as a standard i/o pin or the hsync output from the sync processor. see section 17. input/output (i/o) ports and section 16. sync processor . pte1/hsynco this is a shared function pin. it can be configured as a standard i/o pin or the vsync output from the sync processor. see section 17. input/output (i/o) ports and section 16. sync processor . pte0/sog/tch0 this is a shared function pin. it can be configured as a standard i/o pin, the sog input to the sync processor, or the timer channel 0 i/o pin. see section 17. input/output (i/o) ports , section 16. sync processor , and section 10. timer interface module (tim) . table 1-1. pin functions pin name pin description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC908BD48 ? rev. 2.0 34 general description motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 35 data sheet ? mc68HC908BD48 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 35 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 48,128 bytes of flash memory 1,024 bytes of random-a ccess memory (ram) 26 bytes of user-defined vectors 512 + 470 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented locati on can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 36 memory map motorola 2.4 reserved me mory locations accessing a reserved location can hav e unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserv ed or with the letter r. 2.5 input/output (i/o) section most of the control, st atus, and data registers ar e in the zero page area of $0000?$005f. additional i/o registers have these addresses: $fe00; sim break status register, sbsr $fe01; sim reset status register, srsr $fe02; reserved $fe03; sim break flag co ntrol register, sbfcr $fe04; interrupt stat us register 1, int1 $fe05; interrupt stat us register 2, int2 $fe06; reserved $fe07; flash control register, flcr $fe08; flash block protect register, flbpr $fe09; reserved $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 37 $0000 i/o registers 96 bytes $005f $0060 unimplemented 32 bytes $007f $0080 ram 1,024 bytes $047f $0480 unimplemented 1,920 bytes $0bff $0c00 reserved 256 bytes $0cff $0d00 unimplemented 13,056 bytes $3fff $4000 flash memory 48,128 bytes $fbff $fc00 monitor rom 512 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 38 memory map motorola $fe05 interrupt status register 2 (int2) $fe06 reserved $fe07 flash control register (flcr) $fe08 flash block prot ect register (flbpr) $fe09 reserved $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f reserved $fe10 monitor rom 470 bytes $ffe5 $ffe6 flash vectors 26 bytes $ffff figure 2-1. memory map (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 39 addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: 0 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 00000 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: 00000 ddre2 ddre1 ddre0 write: reset:00000000 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 40 memory map motorola $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000b unimplemented read: write: reset:00000000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 41 $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0016 ddc master control register (dmcr) read: alif nakif bb mast mrw br2 br1 br0 write: reset:00000000 $0017 ddc address register (dadr) read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 $0018 ddc control register (dcr) read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 $0019 ddc status register (dsr) read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 $001a ddc data transmit register (ddtr) read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 $001b ddc data receive register (ddrr) read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 $001c ddc2 address register (d2adr) read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 $001d configuration register 0 (config0) read: hsyncoe vsyncoe soge 00000 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 42 memory map motorola $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 $001f configuration register 1 (config1) ? read: 0000 ssrec coprs stop copd write: reset:00000000 ? one-time writable register after each reset. $0020 pwm0 data register (0pwm) read: 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 write: reset:00000000 $0021 pwm1 data register (1pwm) read: 1pwm4 1pwm3 1pwm2 1pwm1 1pwm0 1brm2 1brm1 1brm0 write: reset:00000000 $0022 pwm2 data register (2pwm) read: 2pwm4 2pwm3 2pwm2 2pwm1 2pwm0 2brm2 2brm1 2brm0 write: reset:00000000 $0023 pwm3 data register (3pwm) read: 3pwm4 3pwm3 3pwm2 3pwm1 3pwm0 3brm2 3brm1 3brm0 write: reset:00000000 $0024 pwm4 data register (4pwm) read: 4pwm4 4pwm3 4pwm2 4pwm1 4pwm0 4brm2 4brm1 4brm0 write: reset:00000000 $0025 pwm5 data register (5pwm) read: 5pwm4 5pwm3 5pwm2 5pwm1 5pwm0 5brm2 5brm1 5brm0 write: reset:00000000 $0026 pwm6 data register (6pwm) read: 6pwm4 6pwm3 6pwm2 6pwm1 6pwm0 6brm2 6brm1 6brm0 write: reset:00000000 $0027 pwm7 data register (7pwm) read: 7pwm4 7pwm3 7pwm2 7pwm1 7pwm0 7brm2 7brm1 7brm0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 43 $0028 pwm control register 1 (pwmcr1) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 $0029 usb address register (uadr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:00000000 $002a usb interrupt register (uintr) read: tbef rbff eopif rstif tbie rbie eopie rstie write: reset:00000000 $002b usb control register 0 (ucr0) read: t0seq stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $002c usb status register (usr) read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: reset: indeterminate after reset $002d usb control register 2 (ucr2) read: 0 0 pullen suspnd enable2 enable1 stall2 stall1 write: reset:00000000 $002e usb interrupt register 1 (uir1) read: txd1f txd1ie resumf00000 write: resumfr tbefr rbffr txd1fr eopfr reset:00000000 $002f usb control register 1 (ucr1) read: t1seq endadd tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $0030 usb endpoint 0 data register 0 (ud0r0) read: ue0rd07 ue0rd06 ue0rd05 ue0rd04 ue0rd03 ue0rd02 ue0rd01 ue0rd00 write: ue0td07 ue0td06 ue0td05 ue0td04 ue0td03 ue0td02 ue0td01 ue0td00 reset: indeterminate after reset $0031 usb endpoint 0 data register 1 (ud0r1) read: ue0rd17 ue0rd16 ue0rd15 ue0rd14 ue0rd13 ue0rd12 ue0rd11 ue0rd10 write: ue0td17 ue0td16 ue0td15 ue0td14 ue0td13 ue0td12 ue0td11 ue0td10 reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 44 memory map motorola $0032 usb endpoint 0 data register 2 (ud0r2) read: ue0rd27 ue0rd26 ue0rd25 ue0rd24 ue0rd23 ue0rd22 ue0rd21 ue0rd20 write: ue0td27 ue0td26 ue0td25 ue0td24 ue0td23 ue0td22 ue0td21 ue0td20 reset: indeterminate after reset $0033 usb endpoint 0 data register 3 (ud0r3) read: ue0rd37 ue0rd36 ue0rd35 ue0rd34 ue0rd33 ue0rd32 ue0rd31 ue0rd30 write: ue0td37 ue0td36 ue0td35 ue0td34 ue0td33 ue0td32 ue0td31 ue0td30 reset: indeterminate after reset $0034 usb endpoint 0 data register 4 (ud0r4) read: ue0rd47 ue0rd46 ue0rd45 ue0rd44 ue0rd43 ue0rd42 ue0rd41 ue0rd40 write: ue0td47 ue0td46 ue0td45 ue0td44 ue0td43 ue0td42 ue0td41 ue0td40 reset: indeterminate after reset $0035 usb endpoint 0 data register 5 (ud0r5) read: ue0rd57 ue0rd56 ue0rd55 ue0rd54 ue0rd53 ue0rd52 ue0rd51 ue0rd50 write: ue0td57 ue0td56 ue0td55 ue0td54 ue0td53 ue0td52 ue0td51 ue0td50 reset: indeterminate after reset $0036 usb endpoint 0 data register 6 (ud0r6) read: ue0rd67 ue0rd66 ue0rd65 ue0rd64 ue0rd63 ue0rd62 ue0rd61 ue0rd60 write: ue0td67 ue0td66 ue0td65 ue0td64 ue0td63 ue0td62 ue0td61 ue0td60 reset: indeterminate after reset $0037 usb endpoint 0 data register 7 (ud0r7) read: ue0rd77 ue0rd76 ue0rd75 ue0rd74 ue0rd73 ue0rd72 ue0rd71 ue0rd70 write: ue0td77 ue0td76 ue0td75 ue0td74 ue0td73 ue0td72 ue0td71 ue0td70 reset: indeterminate after reset $0038 usb endpoint 1/2 data register 0 (ud1r0) read: write: ue1td07 ue1td06 ue1td05 ue1td04 ue1td03 ue1td02 ue1td01 ue1td00 reset: indeterminate after reset $0039 usb endpoint 1/2 data register 1 (ud1r1) read: write: ue1td17 ue1td16 ue1td15 ue1td14 ue1td13 ue1td12 ue1td11 ue1td10 reset: indeterminate after reset $003a usb endpoint 1/2 data register 2 (ud1r2) read: write: ue1td27 ue1td26 ue1td25 ue1td24 ue1td23 ue1td22 ue1td21 ue1td20 reset: indeterminate after reset $003b usb endpoint 1/2 data register 3 (ud1r3) read: write: ue1td37 ue1td36 ue1td35 ue1td34 ue1td33 ue1td32 ue1td31 ue1td30 reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 45 $003c usb endpoint 1/2 data register 4 (ud1r4) read: write: ue1td47 ue1td46 ue1td45 ue1td44 ue1td43 ue1td42 ue1td41 ue1td40 reset: indeterminate after reset $003d usb endpoint 1/2 data register 5 (ud1r5) read: write: ue1td57 ue1td56 ue1td55 ue1td54 ue1td53 ue1td52 ue1td51 ue1td50 reset: indeterminate after reset $003e usb endpoint 1/2 data register 6 (ud1r6) read: write: ue1td67 ue1td66 ue1td65 ue1td64 ue1td63 ue1td62 ue1td61 ue1td60 reset: indeterminate after reset $003f usb endpoint 1/2 data register 7 (ud1r7) read: write: ue1td77 ue1td76 ue1td75 ue1td74 ue1td73 ue1td72 ue1td71 ue1td70 reset: indeterminate after reset $0040 sync processor control and status register (spcsr) read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 $0041 vertical frequency high register (vfhr) read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 $0042 vertical frequency low register (vflr) read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 $0043 hsync frequency high register (hfhr) read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 $0044 hsync frequency low register (hflr) read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 $0045 sync processor i/o control register (spiocr) read: vsyncs hsyncs coinv r sogsel clampoe bpor sout write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 46 memory map motorola $0046 sync processor control register 1 (spcr1) read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:00000000 $0047 h&v sync output control register (hvocr) read: r 0000 hvocr2 hvocr1 hvocr0 write: reset:00000000 $0048 unimplemented read: write: reset: $0049 port d configuration register (pdcr) read: 0 iicdate iicscle clampe ddcscle ddcdate usbd?e usbd+e write: reset:00000000 $004a multi-master iic master control register (mimcr) read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: reset:00000000 $004b multi-master iic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $004c multi-master iic control register (mmcr) read: mmen mmien 00 mmtxak 000 write: reset:00000000 $004d multi-master iic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 $004e multi-master iic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 $004f multi-master iic data receive register (mmdrr) read: mmrd7 mmrd6 mmrd5 mmr d4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 47 $0050 unimplemented read: write: reset: $0051 pwm8 data register (8pwm) read: 8pwm4 8pwm3 8pwm2 8pwm1 8pwm0 8brm2 8brm1 8brm0 write: reset:00000000 $0052 pwm9 data register (9pwm) read: 9pwm4 9pwm3 9pwm2 9pwm1 9pwm0 9brm2 9brm1 9brm0 write: reset:00000000 $0053 pwm10 data register (10pwm) read: 10pwm4 10pwm3 10pwm2 10pwm1 10pwm0 10brm2 10brm1 10brm0 write: reset:00000000 $0054 pwm11 data register (11pwm) read: 11pwm4 11pwm3 11pwm2 11pwm1 11pwm0 11brm2 11brm1 11brm0 write: reset:00000000 $0055 pwm12 data register (12pwm) read: 12pwm4 12pwm3 12pwm2 12pwm1 12pwm0 12brm2 12brm1 12brm0 write: reset:00000000 $0056 pwm13 data register (13pwm) read: 13pwm4 13pwm3 13pwm2 13pwm1 13pwm0 13brm2 13brm1 13brm0 write: reset:00000000 $0057 pwm14 data register (14pwm) read: 14pwm4 pwm3 14pwm2 14pwm1 14pwm0 14brm2 14brm1 14brm0 write: reset:00000000 $0058 pwm15 data register (15pwm) read: 15pwm4 15pwm3 15pwm2 15pwm1 15pwm0 15brm2 15brm1 15brm0 write: reset:00000000 $0059 pwm control register 2 (pwmcr2) read: pwm15e pwm14e pwm13e pwm12e pwm11e pwm10e pwm9e pwm8e write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 48 memory map motorola $005a unimplemented read: write: reset: $005b unimplemented read: write: reset: $005c unimplemented read: write: reset: $005d adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $005e adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected after reset $005f adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset:00000000 note: writing a l ogic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 0 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 10 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 49 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: 0000if10if9if8if7 write:rrrrrrrr reset:00000000 $fe06 reserved read: rrrrrrrr write: reset:00000000 $fe07 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe08 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 $fe09 reserved read: rrrrrrrr write: reset:00000000 $fe0a reserved read: rrrrrrrr write: reset:00000000 $fe0b reserved read: rrrrrrrr write: reset:00000000 $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 11 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 50 memory map motorola $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: writing clears co p counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 12 of 12) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section mc68HC908BD48 ? rev. 2.0 data sheet motorola memory map 51 . table 2-1. vector addresses vector priority int flag address vector lowest ? $ffe6 reserved $ffe7 reserved if10 $ffe8 adc interrupt vector (high) $ffe9 adc interrupt vector (low) if9 $ffea mmiic vector (high) $ffeb mmiic vector (low) if8 $ffec sync processor vector (high) $ffed sync processor vector (low) if7 $ffee tim overflow vector (high) $ffef tim overflow vector (low) if6 $fff0 tim channel 1 vector (high) $fff1 tim channel 1 vector (low) if5 $fff2 tim channel 0 vector (high) $fff3 tim channel 0 vector (low) if4 $fff4 reserved $fff5 reserved if3 $fff6 ddc12ab vector (high) $fff7 ddc12ab vector (low) if2 $fff8 usb vector (high) $fff9 usb vector (low) if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC908BD48 ? rev. 2.0 52 memory map motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola random-access memory (ram) 53 data sheet ? mc68HC908BD48 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2 introduction this section describes the 1, 024 bytes of ram (random-access memory). 3.3 functional description addresses $0080 through $0 47f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 128 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently acce ss all page zero ram locations. page zero ram, therefore, provides i deal locations for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . random-access memory (ram) data sheet mc68HC908BD48 ? rev. 2.0 54 random-access memory (ram) motorola during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola flash memory 55 data sheet ? mc68HC908BD48 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.4 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 56 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 61 4.2 introduction this section describes the operat ion of the embedd ed flash memory. the flash memory can be read, pr ogrammed, and erased from a single external supply through the use of the in ternal charge pump for program and erase. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory data sheet mc68HC908BD48 ? rev. 2.0 56 flash memory motorola 4.3 functional description the flash memory is an array of 48, 128 bytes with an additional 26 bytes of user vectors. an erased bit reads as logic 1 and a programmed bit reads as a logic 0 . program and erase operat ions are facilitated through control bits in a memory mapped flash control register (flcr). the address ranges for t he user memory and vectors are: $4000?$fbff; user memory $fe07; flash control register $fe08; flash block protect register $ffe6?$ffff; these locations are reserved for user-defined interrupt and reset vectors programming tools are available from motorola. contact your local motorola representative for more information. 4.4 flash control register (flcr) the flash control register (flcr) controls flash program and erase operations. address: $fe07 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 4-1. flash cont rol register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash block erase operation mc68HC908BD48 ? rev. 2.0 data sheet motorola flash memory 57 hven ? high-volt age enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operati ons in the array. hv en can only be set if either pgm = 1 or erase = 1 and t he proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configur es the 48,128 bytes flash array for mass erase operation. 1 = mass erase operation selected 0 = mass erase oper ation not selected erase ? erase control bit this read/write bit conf igures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit conf igures the memory fo r program operation. pgm is interlocked with the erase bit such t hat both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation not selected 4.5 flash block erase operation use the following proced ure to erase a block ( 512 bytes) of flash memory: 1. set the erase bit, a nd clear the mass bit in the flash control register. 2. write any data to any flash address within the block address range desired. 3. wait for a time, t nvs (min. 5 s) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory data sheet mc68HC908BD48 ? rev. 2.0 58 flash memory motorola 4. set the hven bit. 5. wait for a time, t erase (min. 2ms) 6. clear the erase bit. 7. wait for a time, t nvh (min. 5 s) 8. clear the hven bit. 9. after a time, t rcv (min. 1 s), the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but ot her unrelated operations may occur between the steps. 4.6 flash mass erase operation use the following pr ocedure to erase ent ire flash memory: 1. set both the erase bit, and the ma ss bit in the flash control register. 2. write any data to any flash address within the flash memory address range. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time, t merase (4ms). 6. clear the erase bit. 7. wait for a time, t nvhl (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s) , the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but ot her unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash program operation mc68HC908BD48 ? rev. 2.0 data sheet motorola flash memory 59 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from a ddresses $xx00, $xx40, $xx80, and $xxc0. use this step-by-s tep procedure to program a row of flash memory ( figure 4-2 is a flowchart representation): note: in order to avoid program disturbs , the row must be erased before any byte on that ro w is programmed. 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write any data to any flash address within t he row address range desired. 3. wait for a time, t nvs (min. 5 s). 4. set the hven bit. 5. wait for a time, t pgs (min. 10 s). 6. write data to the flash address to be programmed. 7. wait for time, t prog (min. 20 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (min. 5 s). 11. clear the hven bit. 12. after time, t rcv (min 1 s), the memory can be accessed in read mode again. this program sequence is repeated th roughout the memory until all data is programmed. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. see 21.15 memory characteristics . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory data sheet mc68HC908BD48 ? rev. 2.0 60 flash memory motorola figure 4-2. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7 to step 7), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash block protection mc68HC908BD48 ? rev. 2.0 data sheet motorola flash memory 61 4.8 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flb pr determines the range of the flash memory which is to be prot ected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or prog ram operations. 4.9 flash block protect register (flbpr) the flash block protect regi ster is implemented as an 7-bit i/o register. the bpr bit content of the register determines t he starting location of the protected range within the flash memory. bpr[7:1] ? flash block protect bits these seven bits represent bits [ 15:9] of a 16-bit memory address. bits [8:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to t he end of flash memory, at $ffff. address: $fe08 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 = unimplemented figure 4-3. flash block pr otect register (flbpr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory data sheet mc68HC908BD48 ? rev. 2.0 62 flash memory motorola figure 4-4. flash block protect start address examples of protect flash memory: bpr[7:0] flash memory protected range $00?3e the entire flash memory is not protected . $40 the entire flash memory is protected. $42 ( 0100 0010 ) $4200 ( 0100 0010 0000 0000) to $ffff $44 ( 0100 0100 ) $4400 ( 0100 0100 0000 0000) to $ffff and so on... $f8 ( 1111 1000 ) $f800 ( 1111 1000 0000 0000) to $ffff $fa ( 1111 1010 )$fa00 ( 1111 1010 0000 0000) to $ffff note: the user flash vectors from $ffe6 to $ffff are always protected, and can only be erased by a flash mass erase operation. flbpr value 16-bit memory address 0000000 start address of flash block protect 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola configuration register (config) 63 data sheet ? mc68HC908BD48 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.3.1 configuration register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.3.2 configuration register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.2 introduction this section describes the config uration registers, config0 and config1. the configuration register s enable or disable these options: sync processor hsynco output pin sync processor vsynco output pin sync processor sog input pin stop mode recovery time (32 oscxclk cycles or 4096 oscxclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 oscxclk cycles) stop instruction computer operating pr operly module (cop) 5.3 functional description the configuration register s are used in the init ialization of various options. the configuratio n registers can be writt en once after each reset. all of the configur ation register bits are cleared during reset. since the various options affect the operation of the mcu, it is recommended that these registers be writ ten immediately after re set. the configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) data sheet mc68HC908BD48 ? rev. 2.0 64 configuration regist er (config) motorola registers are located at $001d and $001f. the configuration register may be read at anytime. 5.3.1 configuration register 0 hsyncoe ? vsynco enable this bit is set to configure the pte1/hsynco pin for hsynco output function. reset clears this bit. 1 = pte1/hsynco pin configured as hsynco pin 0 = pte1/hsynco pi n configured as standard i/o pin vsyncoe ? vsynco enable this bit is set to configure the pte2/vsynco pin fo r vsynco output function. reset clears this bit. 1 = pte2/vsynco pin configured as vsynco pin 0 = pte2/vsynco pi n configured as standard i/o pin soge ? sog enable this bit is set to conf igure the pte0/sog/tch 0 pin for sog output function. reset clears this bit. 1 = pte0/sog/tch0 pin configured as sog pin 0 = pte0/sog/tch0 pin configured as standard i/o or tch0 pin. tch0 function is configured by els0b and els0a bits in tsc0 (bits 3 and 2 in $0010). (see 10.10.4 tim channel status and control r egisters (tsc0:tsc1) .) address: $001d bit 7654321bit 0 read: hsyncoe vsyncoe soge 00000 write: reset:00000000 = unimplemented figure 5-1. configurati on register 0 (config0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola configuration register (config) 65 5.3.2 configuration register 1 ssrec ? short stop recovery bit ssrec enables the cp u to exit stop mode with a delay of 32 oscxclk cycles instead of a 4096-oscxclk cycle delay. 1 = stop mode recovery after 32 os cxclk cycles 0 = stop mode recovery after 4096 oscxclkc cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscillator, do not set the ssrec bit. coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. (see section 19. computer o perating properly (cop) .) 1 = cop timeout period = 2 13 ? 2 4 cgmxclk cycles 0 = cop timeout period = 2 18 ? 2 4 cgmxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 19. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: 0 0 0 0 ssrec coprs stop copd write: reset:00000000 = unimplemented figure 5-2. configurati on register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) data sheet mc68HC908BD48 ? rev. 2.0 66 configuration regist er (config) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 67 data sheet ? mc68HC908BD48 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (motorola document or der number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 68 central processor unit (cpu) motorola 6.3 features object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-regi ster manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressi ng range beyond 64 kbytes low-power stop and wait modes 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 69 figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 70 central processor unit (cpu) motorola 6.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 71 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 72 central processor unit (cpu) motorola 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructi ons bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) arithmetic oper ations. the daa instruction uses the states of the h and c flags to determine t he appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 73 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 74 central processor unit (cpu) motorola c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/l ogic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu during break interrupts mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 75 6.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary 6.9 opcode map see table 6-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 76 central processor unit (cpu) motorola table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) r r ? r r r imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) r r ? r r r imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) r ?? r r r dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right r ?? r r r dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 77 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 78 central processor unit (cpu) motorola brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 79 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? r r 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) r ?? r r r imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? r r r inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 r ?? r r ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? r r inh 52 7 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 80 central processor unit (cpu) motorola eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 r ?? r r ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? r r ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? r r ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) r ?? r r r dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 81 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right r ??0 r r dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? r r ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) r ?? r r r dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? r r ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry r ?? r r r dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 82 central processor unit (cpu) motorola ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry r ?? r r r dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) r r r r r r inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? r r ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? r r ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? r r ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 83 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) r r r r r r inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? r r ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 84 central processor unit (cpu) motorola a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location r set or cleared n negative bit ? not affected table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola central processor unit (cpu) 85 central processor unit (cpu) opcode map table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC908BD48 ? rev. 2.0 86 central processor unit (cpu) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 87 data sheet ? mc68HC908BD48 section 7. system integration module (sim) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 91 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 91 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 93 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 95 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 96 7.5.2 sim counter during stop mode reco very . . . . . . . . . . . . . . 97 7.5.3 sim counter and reset st ates. . . . . . . . . . . . . . . . . . . . . . . 97 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 104 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 88 system integration module (sim) motorola 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 108 7.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 109 7.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 110 7.2 introduction this section describes th e system integration mo dule, which supports up to 16 external and/or internal interrupts. t ogether with the cpu, the sim controls all mcu activities. a blo ck diagram of the sim is shown in figure 7-1 . table 7-1 shows a summary of the sim i/o registers. the sim is a system state controller that coordi nates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals: ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 89 figure 7-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from oscillator) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock oscxclk (from oscillator) 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 90 system integration module (sim) motorola table 7-2 shows the internal signal na mes used in this section. table 7-1. sim i/o register summary addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset:00000000 $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 0 0 write: por:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: 0000if10if9if8if7 write:rrrrrrrr reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved table 7-2. signal name conventions signal name description oscxclk buffered version of osc1 from the oscillator oscout the oscxclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscxclk divided by four) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim bus clock control and generation mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 91 7.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, oscout, as shown in figure 7-2 . figure 7-2. osc clock signals 7.3.1 bus timing in user mode, the inte rnal bus frequency is t he oscillator frequency (oscxclk) divided by four. 7.3.2 clock start-up from por when the power-on reset module generat es a reset, t he clocks to the cpu and peripherals are inactive an d held in an inactive phase until after the 4096 oscxclk cycle por time out has comple ted. the rst is driven low by the sim du ring this entire period. the ibus clocks start upon completion of the timeout. 7.3.3 clocks in stop mode and wait mode upon exit from stop mode (by an interrupt, brea k, or reset), the sim allows oscxclk to clock the si m counter. the cpu and peripheral clocks do not become active until after the stop del ay timeout. this timeout is selectable as 4096 or 32 oscxclk cycles. (see 7.7.2 stop mode .) simoscen oscxclk from sim 2 oscout osc1 osc2 2 bus clock generators sim sim counter oscillator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 92 system integration module (sim) motorola in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 7.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset cl ears the sim counter (see 7.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register (srsr) (see 7.8 sim registers ). 7.4.1 external pin reset pulling the asynchronous rst pin low halts all pr ocessing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 os cxclk cycles, assuming th at the por was the source of the reset (see table 7-3. pin bit set timing) . figure 7-3 shows the relative timing. table 7-3. pin bit set timing reset type number of cycles required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 93 figure 7-3. extern al reset timing 7.4.2 active resets from internal sources sim module in hc08 has the capability to drive the rst pin low when internal reset events occur. all internal reset sour ces actively pull the rst pin low for 32 oscxclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be assert ed for an additi onal 32 cycles (see figure 7- 4. internal reset timing) . an internal reset ca n be caused by an illegal address, illegal opcode, cop timeout, or por (see figure 7-5. sources of internal reset) . note that for por rese ts, the sim cycles through 4096 oscxclk cycles during whic h the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 7-4 . figure 7-4. inter nal reset timing the cop reset is asynchro nous to the bus clock. rst iab pc vect h vect l oscout irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high oscxclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 94 system integration module (sim) motorola figure 7-5. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. 7.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four osc xclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscill ator to drive oscxclk. internal clocks to the cpu and m odules are held i nactive for 4096 oscxclk cycles to allow stab ilization of t he oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. illegal address rst illegal opcode rst coprst por internal reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 95 figure 7-6. por recovery 7.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears th e cop counter and bits 12 through 5 of the sim counter. the s im counter output, which o ccurs at least every 2 12 ? 2 4 oscxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time befor e the first timeout. the cop module is disabled if the rst pin or the irq is held at v tst while the mcu is in monitor m ode. the cop modul e can be disabled only through combinational logic conditioned with the high voltage signal on the rst pin or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. porrst osc1 oscxclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 96 system integration module (sim) motorola 7.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. if the stop enable bit, st op, in the configure r egister 1 (config1) is logic zero, the sim treat s the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 7.4.2.4 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim acti vely pulls down the rst pin for all internal reset sources. 7.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly module (cop). the sim counter overflow supplies the cl ock for the cop module. the sim counter is 12 bits long and is clo cked by the falling edge of oscxclk. 7.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 97 7.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configure register 1 (config1). if the ssrec bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 oscxclk cycles down to 32 oscxclk cycles. thi s is ideal for applications using canned oscillators that do not require long st art-up times from stop mode. external crystal applications should use the full stop recovery time, that is, wi th ssrec cleared. 7.5.3 sim counter and reset states external reset has no ef fect on the sim counter (see 7.7.2 stop mode ). the sim counter is free-running after all reset states ( see 7.4.2 active resets from internal sources for counter control and internal reset recovery sequences). 7.6 exception control normally, sequential program exec ution can be c hanged in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 98 system integration module (sim) motorola 7.6.1 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a parti cular event. figure 7-9 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 7-7 shows interrupt entry timing. figure 7-8 shows interrupt recovery timing. figure 7-7 . interrupt entry figure 7-8. interrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 99 figure 7-9. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? usb interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 100 system integration module (sim) motorola interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrup t may take precedence, regardless of priority, until the latched interrupt is servic ed (or the i bit is cleared). (see figure 7-9. interrupt processing .) 7.6.1.1 hardware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register), and if the corres ponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 7-10 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 7-10 . interrupt recognition example cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 101 the lda opcode is pre- fetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti pre-fetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. 7.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 7.6.2 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 7-4 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 102 system integration module (sim) motorola table 7-4. interrupt sources source flag mask 1 int register flag priority 2 vector address reset none none none 0 $fffe?$ffff swi instruction none none none 0 $fffc?$fffd irq pin irqf imask if1 1 $fffa?$fffb usb tbef tbie if2 2 $fff8?$fff9 rbff rbie eopif eopie rstif rstie txd1f txd1ie ddc12ab alif dien if3 3 $fff6?$fff7 nakif rxif txif sclif sclien reserved ? ? ? ? $fff4?$fff5 tim channel 0 ch0f ch0ie if5 5 $fff2?$fff3 tim channel 1 ch1f ch1ie if6 6 $fff0?$fff1 tim overflow tof toie if7 7 $ffee?$ffef sync processor vsif vsie if8 8 $ffec?$ffed lvsif lvsie multi-master iic mmalif mmien if9 9 $ffea?ffeb mmnakif mmrxif mmtxif adc conversion complete coco aien if10 10 $ffe8?$ffe9 reserved ? ? ? ? $ffe6?$ffe7 1. the i bit in the condition code register is a global mask for all interrupts source s except the swi instruction. 2. 0 = highest priority f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 103 7.6.2.1 interrupt status register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 7-4 . 1 = interrupt request present 0 = no interrupt request present bit 1and bit 0 ? always read 0 7.6.2.2 interrupt status register 2 if10?if7 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 7-4 . 1 = interrupt request present 0 = no interrupt request present bit 7 and bit 4 ? always read 0 address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 7-11. interrupt st atus register 1 (int1) address: $fe05 bit 7654321bit 0 read: 0000if10if9if8if7 write:rrrrrrrr reset:00000000 r= reserved figure 7-12. interrupt st atus register 2 (int2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 104 system integration module (sim) motorola 7.6.3 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 7.6.4 break interrupts the break module can st op normal program flow at a software- programmable break point by assert ing its break interrupt output (see section 20. break module (brk) ). the sim puts t he cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 7.6.5 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in t he sim break flag contro l register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing st atus flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step cleari ng mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 105 7.7 low-power modes executing the wait or stop instruction puts t he mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 7.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 7-13 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in configuration register 1 (config1) is logic zero, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 7-13. wait mode entry timing figure 7-14 and figure 7-15 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 106 system integration module (sim) motorola figure 7-14. wait recovery from interrupt or break figure 7-15. wait recover y from internal reset 7.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the oscillator si gnals (oscout and oscxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in configuration r egister 1 (config1). if ssrec is set, stop recovery is reduced from the nor mal delay of 4096 oscxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require lo ng start-up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 oscxclk 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 107 a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the sim break st atus register (sbsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 7-16 shows stop mode entry timing. figure 7-16. stop mode entry timing figure 7-17. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. oscxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 108 system integration module (sim) motorola 7.8 sim registers the sim has three memo ry mapped registers. table 7-5 shows the mapping of thes e registers. 7.8.1 sim break status register (sbsr) the sim break status register contains a flag to indica te that a break caused an exit from st op or wait mode. sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt table 7-5. sim registers summary address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset:00000000 note: writing a logic 0 clears sbsw. r= reserved figure 7-18. sim break stat us register (sbsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68HC908BD48 ? rev. 2.0 data sheet motorola system integration module (sim) 109 sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. 7.8.2 sim reset status register (srsr) this register contains six flags that show the sour ce of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clear s all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 0 0 write: por:10000000 = unimplemented figure 7-19. sim reset status register (srsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC908BD48 ? rev. 2.0 110 system integration module (sim) motorola pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr 7.8.3 sim break flag control register (sbfcr) the sim break flag control r egister contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 7-20. sim break flag c ontrol register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola oscillator (osc) 111 data sheet ? mc68HC908BD48 section 8. oscillator (osc) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.3 oscillator external connections . . . . . . . . . . . . . . . . . . . . . . .112 8.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 113 8.4.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 113 8.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 113 8.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . 113 8.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.2 introduction the oscillator circuit is designed for use with crystals or ceramic resonators. the oscillat or circuit generates the crystal clock signal, oscxclk, at the frequency of the crystal. this signal is divided by two before being passed on to the si m for bus clock generation. figure 8-1 shows the structure of the oscillator. the oscill ator requires various external components. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) data sheet mc68HC908BD48 ? rev. 2.0 112 oscillator (osc) motorola 8.3 oscillator ex ternal connections in its typical configur ation, the oscillator requires five external components. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 8-1 . this figure shows only the logical representat ion of the internal components and may not represent actual circui try. the oscillator conf iguration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. figure 8-1. oscillator external connections c 1 c 2 simoscen oscxclk r b x 1 r s * *r s can be zero (shorted) when used with mcu from sim 2 oscout to sim to sim osc1 osc2 higher-frequency crystals. refer to manufacturer?s data. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) i/o signals mc68HC908BD48 ? rev. 2.0 data sheet motorola oscillator (osc) 113 8.4 i/o signals the following paragraphs describe the oscillator i/o signals. 8.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. an externally generated cl ock also can feed the os c1 pin of the crystal oscillator circuit. connect the exter nal clock to the o sc1 pin and let the osc2 pin float. 8.4.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 8.4.3 oscillator enable signal (simoscen) the simoscen signal comes from the sim and enabl es the oscillator. 8.4.4 external clock source (oscxclk) oscxclk is the crystal oscillator out put signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 8-1 shows only the logical rela tion of oscxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of oscxclk is unknown and may d epend on the crystal and other external factors. also, the frequen cy and amplitude of oscxclk can be unstable at start-up. 8.4.5 oscillator out (oscout) the clock driven to the si m is the crystal frequency divided by two. this signal is driven to the sim for genera tion of the bus clocks used by the cpu and other modules on the mcu. oscout will be divided again in the sim and results in th e internal bus frequency being one four th of the oscxclk frequency. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) data sheet mc68HC908BD48 ? rev. 2.0 114 oscillator (osc) motorola 8.5 low power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 8.5.1 wait mode the wait instruction has no effect on the osci llator logic. oscxclk continues to drive to the sim module. 8.5.2 stop mode the stop instructio n disables the oscxclk output. 8.6 oscillator during break mode the oscillator continues drive oscxclk when the ch ip enters the break state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola monitor rom (mon) 115 data sheet ? mc68HC908BD48 section 9. monitor rom (mon) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 9.2 introduction this section describes the monito r rom. the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC908BD48 ? rev. 2.0 116 monitor rom (mon) motorola 9.3 features features of the mo nitor rom include: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer 9600 baud communicati on with host computer execution of code in ram or flash flash memory programming 9.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 9-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can exec ute host-computer code in ram while all mcu pins retain normal operating mode functions. all communication between the host computer and the m cu is through the pta0 pin. a level-shifting and multiplexing in terface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pull-up resistor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola monitor rom (mon) 117 figure 9-1. monitor mode circuit 10 m ? x1 v dd 68HC908BD48 rst irq osc1 osc2 v ss v dd pta0 v dd 10 k ? 0.1 f v dd 20 pf 20 pf 0.1 f 9.83 mhz 10 k ? ptc3 v dd 10 k ? b a notes: position b ? bus clock = oscxclk 2 (see notes) ptc0 ptc1 v dd 10 k ? position a ? bus clock = oscxclk 4 v ss1 pta7 16 15 2 6 v dd max232 v+ v? v dd 10 k c1+ c1? 5 4 c2+ c2? + 3 1 1 f + + + 8 7 db9 2 3 5 10 9 + 1 2 3 4 5 6 74hc125 74hc125 1 k v tst v cc gnd 1 f 1 f 1 f 1 f 8.5 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC908BD48 ? rev. 2.0 118 monitor rom (mon) motorola 9.4.1 entering monitor mode table 9-1 shows the pin conditions for entering monitor mode. note: holding the ptc3 pin low when ent ering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the oscout frequency is equal to the oscxclk frequency, and the osc1 input directly generates internal bus clocks. in th is case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. enter monitor mode with the pin co nfiguration shown above by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is la tched, the values on th e specified pins can change. once out of reset, t he mcu monitor mode firmwa re then sends a break signal (10 consecutive logi c zeros) to the host co mputer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow t he host to determine t he necessary baud rate. monitor mode uses differ ent vectors for reset and swi. the alternate vectors are in the $fe page in stead of the $ff page and allow code execution from the internal monito r firmware instead of user code. when the host computer has comple ted downloading code into the mcu ram, this code can be executed by driving pta0 low while asserting rst low and then high. the internal monitor rom fi rmware will interpret the low on pta0 as an i ndication to jump to ra m, and execution control will then continue from ram. execution of an swi from the downloaded code will return program control to the internal monitor rom firmware. table 9-1. mode selection irq pin ptc0 pin ptc1 pin pta7 pin pta0 pin ptc3 pin mode oscout bus frequency v tst 10011 monitor v tst 10010 monitor oscxclk oscxclk 2 ---------------------------- oscxclk 4 ---------------------------- oscxclk 2 ---------------------------- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola monitor rom (mon) 119 alternatively, the host can send a run command, whic h executes an rti, and this can be used to send control to the addr ess on the stack pointer. the cop module is disabled in monitor mode as long as v tst is applied to the irq or the rst pin. (see section 7. system integration module (sim) for more information on modes of operation.) table 9-2 is a summary of the diff erences between user mode and monitor mode. 9.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 9-2 and figure 9-3 .) figure 9-2. monitor data format figure 9-3. sample monitor waveforms table 9-2. mode differences modes functions cop reset vector high reset vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd monitor disabled (1) notes : 1. if the high voltage (v tst ) is removed from the irq pin, the sim asserts its cop enable output. the cop is a mask option enabled or disa bled by the copd bit in the configuration register. $fefe $feff $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 stop bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC908BD48 ? rev. 2.0 120 monitor rom (mon) motorola the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. 9.4.3 echoing as shown in figure 9-4 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. figure 9-4. read transaction any result of a command appears after the ec ho of the last byte of the command. 9.4.4 break signal a start bit followed by nine low bits is a break signal (see figure 9-5 ). when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. figure 9-5. br eak transaction addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola monitor rom (mon) 121 9.4.5 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) table 9-3. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence read read echo sent to monitor address high address high address low data return address low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC908BD48 ? rev. 2.0 122 monitor rom (mon) motorola table 9-4. write (write memory) command description write byte to memory operand specifics 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence table 9-5. iread (i ndexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo sent to monitor address high address high address low address low data data iread iread echo sent to monitor data return data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola monitor rom (mon) 123 a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64-kbyte memory map. table 9-6. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence table 9-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence iwrite iwrite echo sent to monitor data data readsp readsp echo sent to monitor sp return sp high low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC908BD48 ? rev. 2.0 124 monitor rom (mon) motorola 9.4.6 baud rate the communication baud rate is cont rolled by crystal frequency and the state of the ptc3 pin upon entry into monitor mode. when ptc3 is high, the divide by ratio is 1024. if the ptc3 pin is at logic zero upon entry into monitor mode, the divi de by ratio is 512. table 9-8. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 9-9. monitor baud rate selection crystal frequency ptc3 pin baud rate 19.66 mhz 0 19200 bps 9.83 mhz 0 9600 bps 9.83 mhz 1 4800 bps f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 125 data sheet ? mc68HC908BD48 section 10. timer interface module (tim) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 130 10.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .131 10.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 131 10.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 132 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 133 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 10.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 137 10.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 139 10.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 140 10.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 141 10.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 145 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 126 timer interface module (tim) motorola 10.2 introduction this section describes th e timer interface module (tim2, version b). the tim is a two-channel time r that provides a timi ng reference with input capture, output compar e, and pulse-width-m odulation functions. figure 10-1 is a block diagr am of the tim. 10.3 features features of the tim include the following: two input capture/ou tput compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input with 7-frequency internal bus clock prescaler selection free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits note: tch1 (timer channel 1) is not bonded to an external pin on this mcu. therefore, any references to the ti mer tch1 pin in the following text should be interpreted as not available ? but the inter nal status and control registers ar e still available. 10.4 pin name conventions the tim share one i/o pi n with one port e i/o pin. the full name of the tim i/o pin is listed in table 10-1 . the generic pin nam e appear in the text that follows. table 10-1. pin name conventions tim generic pin names: tch0 tch1 full tim pin names: pte0/sog/tch0 not available f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 127 10.5 functional description figure 10-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels are program mable independently as input capture or output compare channels. figure 10-1. tim block diagram prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a interrupt logic port logic interrupt logic interrupt logic port logic tch1 tch0 (not available) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 128 timer interface module (tim) motorola table 10-2. tim i/o register summary addr.register name bit 7654321bit 0 $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status/control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status/control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 129 10.5.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rate s from the internal bus clock. the prescaler select bits, ps[2:0], in t he tim status and control register (tsc) select the tim clock source. 10.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 10.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 130 timer interface module (tim) motorola 10.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow perio d. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 131 10.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enabl es the tim channel 1 registers to synchronously control t he output after the tim overflows. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the output are the ones writte n to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 10.5.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 10-2 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic one. program the tim to set the pin if the state of the pwm pulse is logic zero. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 132 timer interface module (tim) motorola figure 10-2. pwm peri od and pulse width the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is 000 (see 10.10.1 tim status and control register (tsc) ). the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 10.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 10.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 133 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger val ue in an output compare interrupt routine (at the end of the current pulse) c ould cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 10.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel re gisters of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writ ing to the tim channel 1 registers enables the ti m channel 1 registers to synchronously control the pulse width at t he beginning of the nex t pwm period. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the pulse width are the ones written to last. tsc0 c ontrols and monitors the buffered pwm functi on, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 134 timer interface module (tim) motorola note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. user so ftware should track the currently active channel to prevent writing a new value to the active channel. writing to the active c hannel registers is the same as generating unbuffer ed pwm signals. 10.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter and pre scaler by setting the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 10-4 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 10-4 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) interrupts mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 135 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim channel 0 status and control register (tsc0) controls and monito rs the pwm signal from the linked channels. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 10.10.4 tim channel status and control registers (tsc0:tsc1) . 10.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overfl ow interrupt enable bit, toie, enables tim overflow cpu interr upt requests. tof and toie are in the tim status and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxie=1. chxf and chxie ar e in the tim channel x status and control register. 10.7 wait mode the wait instruction puts the mcu in low-power-consumption standby mode. the tim remains active after the executi on of a wait instru ction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 136 timer interface module (tim) motorola 10.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the break flag control regi ster (bfcr) enables software to clear status bits during the break state. (see 7.8.3 sim break flag control register (sbfcr) .) to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 10.9 i/o signals port e shares one of it s pins with the tim. the tim channel i/o pin is pte0/sog/tch0. tch0 pin is programmable independently as an input capture pin or an output compare pin. it also can be configur ed as a buffered output compare or buffered pwm pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 137 10.10 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0 and tsc1) tim channel registers (tch 0h:tch0l and tch1h:tch1l) 10.10.1 tim status and control register (tsc) the tim status and control r egister does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when t he tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register w hen tof is set and then writing a logic zero to tof. if anot her tim overflow oc curs before the address: $000a bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 10-3. tim st atus and control register (tsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 138 timer interface module (tim) motorola clearing sequence is complete, then wr iting logic zero to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is rese t and always reads as l ogic zero. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the tclk pin or one of the seven prescaler outputs as the i nput to the tim counter as table 10-3 shows. reset clears the ps[2:0] bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 139 10.10.2 tim counter registers (tcnth:tcntl) the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. table 10-3. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 not available f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 140 timer interface module (tim) motorola 10.10.3 tim counter modulo registers (tmodh:tmodl) the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow inte rrupts until the low byte (tmodl) is written. reset sets the ti m counter modulo registers. address: $000c tcnth bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 address: $000d tcntl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 = unimplemented figure 10-4. tim counter registers (tcnth:tcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 141 note: reset the tim counter bef ore writing to the tim counter modulo registers. 10.10.4 tim channel status and control registers (tsc0:tsc1) each of the tim channel status and control regi sters does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 0% and 1 00% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation address: $000e tmodh bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 address: $000f tmodl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 10-5. tim counter modu lo registers (tmodh:tmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 142 timer interface module (tim) motorola chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests are enabled (chxie=1), clear chxf by reading the tim channel x status an d control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset cl ears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled address: $0010 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0013 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 10-6. tim channel status and control registers (tsc0:tsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 143 msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 10-4 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 00, this read/write bit selects the in itial output level of the tchx pin. (see table 10-4 .). reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to an i/o port , and pi n tchx is available as a general-purpose port i/o pin. table 10-4 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 144 timer interface module (tim) motorola note: before enabling a tim ch annel register for input capture operation, make sure that the tchx pin is st able for at leas t two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not t oggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic one, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 10-7 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 10-4. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC908BD48 ? rev. 2.0 data sheet motorola timer interface module (tim) 145 figure 10-7. chxmax latency 10.10.5 tim channel registers (tch0h/l:tch1h/l) these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. output overflow ptdx/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC908BD48 ? rev. 2.0 146 timer interface module (tim) motorola address: $0011 tch0h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0012 tch0l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset address: $0014 tch1h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0015 tch1l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset figure 10-8. tim channel regi sters (tch0h/l:tch1h/l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola pulse width modulator (pwm) 147 data sheet ? mc68HC908BD48 section 11. pulse width modulator (pwm) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.4 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.4.1 pwm data registers 0 to 15 (0pwm?15pwm). . . . . . . . . 150 11.4.2 pwm control registers 1 and 2 (pwmcr1:pwmcr2) . . 151 11.2 introduction sixteen 8-bits pwm channels are available on the mc68HC908BD48. channels 0 to 7 are shared with port- b i/o pins under t he control of the pwm control register 1. channels 8 to 15 are shared with port-a i/o pins under the control of the pwm control register 2. 11.3 functional description each 8-bit pwm channel is composed of an 8-bit register which contains a 5-bit pwm in m sb portion and a 3-bit binary rate multiplier (brm) in lsb portion. there are 16 pwm data registers as shown in table 11-1 . the value programmed in the 5-bit pw m portion will de termine the pulse length of the output. the clock to th e 5-bit pwm portion is the system clock, the repetition rate of the out put is hence 187.5khz at 6mhz clock. the 3-bit brm will generate a number of narro w pulses which are equally distributed among an 8-pwm-cy cle frame. the number of pulses generated is equal to the number program med in the 3-bit brm portion. examples of the waveforms are shown in figure 11-3 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator (pwm) data sheet mc68HC908BD48 ? rev. 2.0 148 pulse width modulator (pwm) motorola combining the 5-bit pwm together wit h the 3-bit brm, the average duty cycle at the output will be (m+n/8)/32, where m is the cont ent of the 5-bit pwm portion, and n is t he content of the 3-bit brm portion. using this mechanism, a true 8-bit resolution pwm type dac with reasonably high repetition rate can be obtained. the value of each pwm data register is continuously compared with the content of an internal counter to determine the st ate of each pwm channel output pin. double buffering is not used in this pwm design. table 11-1. pwm i/o register summary addr.register name bit 7654321bit 0 $0020 pwm0 data register (0pwm) read: 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 write: $0021 pwm1 data register (1pwm) read: 1pwm4 1pwm3 1pwm2 1pwm1 1pwm0 1brm2 1brm1 1brm0 write: $0022 pwm2 data register (2pwm) read: 2pwm4 2pwm3 2pwm2 2pwm1 2pwm0 2brm2 2brm1 2brm0 write: $0023 pwm3 data register (3pwm) read: 3pwm4 3pwm3 3pwm2 3pwm1 3pwm0 3brm2 3brm1 3brm0 write: $0024 pwm4 data register (4pwm) read: 4pwm4 4pwm3 4pwm2 4pwm1 4pwm0 4brm2 4brm1 4brm0 write: $0025 pwm5 data register (5pwm) read: 5pwm4 5pwm3 5pwm2 5pwm1 5pwm0 5brm2 5brm1 5brm0 write: $0026 pwm6 data register (6pwm) read: 6pwm4 6pwm3 6pwm2 6pwm1 6pwm0 6brm2 6brm1 6brm0 write: $0027 pwm7 data register (7pwm) read: 7pwm4 7pwm3 7pwm2 7pwm1 7pwm0 7brm2 7brm1 7brm0 write: $0028 pwm control register 1 (pwmcr1) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator (pwm) pwm registers mc68HC908BD48 ? rev. 2.0 data sheet motorola pulse width modulator (pwm) 149 11.4 pwm registers the pwm module uses of 18 registers for data an d control functions. 16 pwm data register s ($0020?$0027 and $0051?$0058) 2 pwm control r egisters ($0028 and $0059) $0051 pwm8 data register (8pwm) read: 8pwm4 8pwm3 8pwm2 8pwm1 8pwm0 8brm2 8brm1 8brm0 write: $0052 pwm9 data register (9pwm) read: 9pwm4 9pwm3 9pwm2 9pwm1 9pwm0 9brm2 9brm1 9brm0 write: $0053 pwm10 data register (10pwm) read: 10pwm4 10pwm3 10pwm2 10pwm1 10pwm0 10brm2 10brm1 10brm0 write: $0054 pwm11 data register (11pwm) read: 11pwm4 11pwm3 11pwm2 11pwm1 11pwm0 11brm2 11brm1 11brm0 write: $0055 pwm12 data register (12pwm) read: 12pwm4 12pwm3 12pwm2 12pwm1 12pwm0 12brm2 12brm1 12brm0 write: $0056 pwm13 data register (13pwm) read: 13pwm4 13pwm3 13pwm2 13pwm1 13pwm0 13brm2 13brm1 13brm0 write: $0057 pwm14 data register (14pwm) read: 14pwm4 pwm3 14pwm2 14pwm1 14pwm0 14brm2 14brm1 14brm0 write: $0058 pwm15 data register (15pwm) read: 15pwm4 15pwm3 15pwm2 15pwm1 15pwm0 15brm2 15brm1 15brm0 write: $0059 pwm control register 2 (pwmcr2) read: pwm15e pwm14e pwm13e pwm12e pwm11e pwm10e pwm9e pwm8e write: table 11-1. pwm i/o register summary reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator (pwm) data sheet mc68HC908BD48 ? rev. 2.0 150 pulse width modulator (pwm) motorola 11.4.1 pwm data registers 0 to 15 (0pwm?15pwm) the output waveform of the 16 pwm channels are each configured by an 8-bit register, which contains a 5-bit pwm in msb portion and a 3-bit binary rate multiplier (brm) in lsb portion xpwm4?xpwm0 ? pwm bits the value programmed in the 5-bit pw m portion will de termine the pulse length of the output. the clock to th e 5-bit pwm portion is the system clock (cpu clock), the repetition rate of the out put is hence f op 32. examples of pwm output waveforms are shown in figure 11-3 . xbrm2?xbrm0 ? binary rate multiplier bits the 3-bit brm will generate a number of narro w pulses which are equally distributed among an 8-pwm-cy cle frame. the number of pulses generated is equal to the number program med in the 3-bit brm portion. examples of pwm output waveforms are shown in figure 11-3 . address: $0020?$0027 and $0051?$0058 bit 7654321bit 0 read: xpwm4 xpwm3 xpwm2 xpwm1 xpwm0 xbrm2 xbrm1 xbrm0 write: reset:00000000 figure 11-1. pwm data regi sters 0 to 15 (0pwm?15pwm) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator (pwm) pwm registers mc68HC908BD48 ? rev. 2.0 data sheet motorola pulse width modulator (pwm) 151 11.4.2 pwm control registers 1 and 2 (pwmcr1:pwmcr2) pwm15e?pwm0e ? pw m output enable setting a bit to 1 will enable th e corresponding pwm channel to use as pwm output. a zero configures the corresponding pwm pin as a standard i/o port pin. re set clears these bits. 1 = port pin configured as pwm output 0 = port pin configured as standard i/o port pin. $0028 pwm control register 1 (pwmcr1) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: $0059 pwm control register 2 (pwmcr2) read: pwm15e pwm14e pwm13e pwm12e pwm11e pwm10e pwm9e pwm8e write: reset:00000000 figure 11-2. pwm control regi ster 1 and 2 (p wmcr1:pwmcr2) table 11-2. pwm channel s and port i/o pins port pin pwm channel control bit port pin pwm channel control bit ptb0 pwm0 pwm0e pta0 pwm8 pwm8e ptb1 pwm1 pwm1e pta1 pwm9 pwm9e ptb2 pwm2 pwm2e pta2 pwm10 pwm10e ptb3 pwm3 pwm3e pta3 pwm11 pwm11e ptb4 pwm4 pwm4e pta4 pwm12 pwm12e ptb5 pwm5 pwm5e pta5 pwm13 pwm13e ptb6 pwm6 pwm6e pta6 pwm14 pwm14e ptb7 pwm7 pwm7e pta7 pwm15 pwm15e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator (pwm) data sheet mc68HC908BD48 ? rev. 2.0 152 pulse width modulator (pwm) motorola figure 11-3. 8-bit pwm output waveforms m=$00 1 pwm cycle = 32t m=$01 m=$0f m=$1f t=1 cpu clock period (0.167 s if cpu clock=6mhz) pulse inserted at end of pwm cycle n pwm cycles where pulses are inserted in a 8-cycle frame number of inserted pulses in a 8-cycle frame xx1 4 1 x1x 2, 6 2 1xx 1, 3, 5, 7 4 31t 16t 16t 31t t m = value set in 5-bit pwm (bit3-bit7) n = value set in 3-bit brm (bit0-bit2) t depends on setting of n. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola analog-to-digit al converter (adc) 153 data sheet ? mc68HC908BD48 section 12. analog-to-digital converter (adc) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 12.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 12.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 12.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 12.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 12.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.7.1 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 12.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .158 12.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.2 introduction this section describes the analog-to-digital converter (adc). the adc is an 8-bit 6-channels anal og-to-digital converter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68HC908BD48 ? rev. 2.0 154 analog-to-digital converter (adc) motorola 12.3 features features of the ad c module include: 6 channels adc with multiplexed input linear successive approximation 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 12.4 functional description six adc channels are avail able for sampling exter nal sources at pins ptc5?ptc0. an analog multiplexer al lows the single adc converter to select one of the 6 ad c channels as adc volt age input (adcvin). adcvin is converted by the successi ve approximation register-based counters. the adc resolu tion is 8 bits. when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 12-1 shows a block diagram of the adc. table 12-1. adc register summary addr.register name bit 7654321bit 0 $005d adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $005e adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $005f adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola analog-to-digit al converter (adc) 155 figure 12-1. adc block diagram 12.4.1 adc port i/o pins ptc5?ptc0 are general-purpos e i/o pins that are shared with the adc channels. the channel select bits (adc status co ntrol register, $005d), define which adc channel/port pin wi ll be used as t he input signal. the adc overrides the port i/ o logic by forcing that pin as input to the adc. the remaining adc channels/ port pins are controlled by the port i/o logic and can be used as general-purpose i/ o. writes to the port register internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock adch[4:0] adc data register adiv[2:0] aien coco disable disable adc channel x read ddrc write ddrc reset write ptc read ptc ptcx/adcx ddrcx ptcx (1 of 6 channels) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68HC908BD48 ? rev. 2.0 156 analog-to-digital converter (adc) motorola or ddr will not have any af fect on the port pin t hat is selected by the adc. read of a port pi n which is in use by the adc will return an unknown state if the corre sponding ddr bit is at lo gic 0. if the ddr bit is at logic 1, the value in the port data latch is read. 12.4.2 voltage conversion when the input voltage to the adc equals v dd , the adc converts the signal to $ff (full scale). if the input voltage equals v ss , the adc converts it to $00. input voltage between v dd and v ss are a straight-line linear conver sion. all other input volt ages will result in $ff if greater than v dd and $00 if less than v ss . note: input voltage should not exceed the analog supply voltages. 12.4.3 conversion time twelve adc internal cl ocks are required to perf orm one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a wr ite to the adscr. if the adc internal clock is selected to run at 1mhz, then one conversion will take 12 s to complete. with a 1mhz adc internal clock t he maximum sample rate is 83.3khz. 12.4.4 continuous conversion in the continuous conv ersion mode, the adc cont inuously converts the selected channel filling t he adc data register wi th new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not . conversions will continue until the adco bit is clear ed. the coco bit (adc st atus control register, $005d) is set after each conversion and can be cleared by writing the adc status and control register or reading of the adc data register. 2 3 ------ - 2 3 ------ - 2 3 ------ - 12 adc clock cycles conversion time = adc clock frequency number of bus cycles = conversion time bus frequency f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) interrupts mc68HC908BD48 ? rev. 2.0 data sheet motorola analog-to-digit al converter (adc) 157 12.4.5 accuracy and precision the conversion process is monot onic and has no missing codes. 12.5 interrupts when the aien bit is se t, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 12.6 low-power modes the following subsections descr ibe the low-power modes. 12.6.1 wait mode the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by se tting the adch[4:0] bits in the adc status and control register to l ogic 1?s before executi ng the wait instruction. 12.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conver sions resume when the mcu exits stop mode. allow one conver sion cycle to stabilize the analog circuitry before attempting a new adc conversion af ter exiting stop mode. 12.7 i/o signals the adc module has 6 c hannels that are shared with i/o port c. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68HC908BD48 ? rev. 2.0 158 analog-to-digital converter (adc) motorola 12.7.1 adc voltage in (adcvin) adcvin is the input voltage signal from one of the 6 adc channels to the adc module. 12.8 i/o registers three i/o registers control and monitor adc operation: adc status and control register (a dscr, $005d) adc data register (adr, $005e) adc clock register (adiclk, $005f) 12.8.1 adc status and control register the following paragraphs describe the function of the adc status and control register. coco ? conversions complete bit when the aien bit is a l ogic 0, the coco is a read-only bit which is set each time a conversion is comple ted. this bit is cleared whenever the adc status and contro l register is writt en or whenever the adc data register is read. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not co mpleted (aien = 0) when the aien bit is a logic 1 (cpu interrupt enabled), the coco is a read-only bit, and will always be lo gic 0 when read. address: $005d bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 12-2. adc status and contro l register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68HC908BD48 ? rev. 2.0 data sheet motorola analog-to-digit al converter (adc) 159 aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status/control register is written. re set clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels. the five channel select bits are detailed in the following table. care should be taken when us ing a port pin as both an analog and a digital input simu ltaneously to prevent switching noise from corrupting the analog signal. (see table 12-2 .) the adc subsystem is turned off w hen the channel select bits are all set to one. this feature allows fo r reduced power consumption for the mcu when the adc is not used. reset sets all of these bits to a logic 1. note: recovery from the disabled stat e requires one conversion cycle to stabilize. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68HC908BD48 ? rev. 2.0 160 analog-to-digital converter (adc) motorola 12.8.2 adc data register one 8-bit result register is provi ded. this register is updated each time an adc conversion completes. table 12-2. mux channel select adch4 adch3 adch2 adch1 adch0 adc channel input select 00000adc0 ptc0 00001adc1 ptc1 00010adc2 ptc2 00011adc3 ptc3 00100adc4 ptc4 00101adc5 ptc5 00110 unused (see note 1) ::::: ? 11010 11011 ? reserved 11 1 0 0 ? unused 11 1 0 1 v dda (see note 2) 11 1 1 0 v ssa (see note 2) 11 1 1 1 adc power off notes: 1. if any unused channels are selected, the resulting adc conversion will be unknown. 2. the voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the adc converter both in pr oduction test and for user applications. address: $005e bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 12-3. adc data register (adr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68HC908BD48 ? rev. 2.0 data sheet motorola analog-to-digit al converter (adc) 161 12.8.3 adc input clock register this register selects the clock frequency for the adc. adiv2:adiv0 ? adc cl ock prescaler bits adiv2, adiv1, and adiv0 form a 3-bit field wh ich selects the divide ratio used by the adc to generat e the internal adc clock. table 12-3 shows the available clock confi gurations. the adc clock should be set to approximately 1mhz. with an internal bus frequency of 6mhz, set adiv[2:0] = 010, for a divi de by four adc clock rate. address: $005f bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 12-4. adc input cl ock register (adiclk) table 12-3. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 x x internal bus clock 16 x = don?t care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) data sheet mc68HC908BD48 ? rev. 2.0 162 analog-to-digital converter (adc) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 163 data sheet ? mc68HC908BD48 section 13. universal serial bus module (usb) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 13.5 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 13.5.1 usb address register (uadr) . . . . . . . . . . . . . . . . . . . . . 166 13.5.2 usb interrupt register (uintr). . . . . . . . . . . . . . . . . . . . . 166 13.5.3 usb interrupt register 1 (uir1). . . . . . . . . . . . . . . . . . . . . 169 13.5.4 usb control register 0 (ucr0). . . . . . . . . . . . . . . . . . . . . 171 13.5.5 usb control register 1 (ucr1). . . . . . . . . . . . . . . . . . . . . 172 13.5.6 usb control register 2 (ucr2). . . . . . . . . . . . . . . . . . . . . 174 13.5.7 usb status register (usr) . . . . . . . . . . . . . . . . . . . . . . . . 175 13.5.8 usb endpoint 0 da ta registers 0 to 7 (ud0r0?ud0r7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.5.9 usb endpoint 1/2 da ta registers 0 to 7 (ud1r0?ud1r7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.2 introduction this usb module is des igned to serve as a lo w-speed (ls) usb device per the universal serial bus specification rev 1.0. three types of usb data tr ansfers are supported: c ontrol, interrupt, and bulk (transmit only). endpoi nt 0 functions as a receive/transmit control endpoint. endpoints 1 and 2 can function as interrupt or bulk, but only in transmit direction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 164 universal serial bus module (usb) motorola 13.3 features features of the usb (uni versal serial bus) module include the following: integrated 3.3-volt regulato r with 3.3-vo lt output pin integrated usb transceiver s upporting low-speed functions usb data control logic ? packet decoding/generation ? crc (cyclic redundancy che ck) generation and checking ? nrzi (non-return-to zero inserted) encoding/decoding ? bit-stuffing usb reset support control endpoint 0 and in terrupt endpoints 1 and 2 two 8-byte transmit buffers one 8-byte receive buffer suspend and resume operations ? remote wakeup support usb generated interrupts ? transaction interrupt driven ? resume interrupt ? end-of-pack (eop) interrupt stall, nak, and a ck handshake generation 13.4 i/o pins the usb module uses two i/o pins, s hared with standard port i/o pins. the full name of the usb i/o pins are listed in table 13-1 . the generic pin name appear in the text that follows. table 13-1. pin name conventions usb generic pin names: full mcu pin names: pin selected for usb function by: d+ ptd0/d+ usbd+e bit in pdcr ($0049) d? ptd1/d? usbd?e bit in pdcr ($0049) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 165 13.5 registers there are seven control/status regist ers and 24 data buffers in the usb module. these register s are discussed in the following paragraphs. table 13-2. usb i/o register summary addr.register name bit 7654321bit 0 $0029 usb address register (uadr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:00000000 $002a usb interrupt register (uintr) read: tbef rbff eopif rstif tbie rbie eopie rstie write: reset:00000000 $002b usb control register 0 (ucr0) read: t0seq stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $002c usb status register (usr) read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: reset: indeterminate after reset $002d usb control register 2 (ucr2) read: 0 0 pullen suspnd enable2 enable1 stall2 stall1 write: reset:00000000 $002e usb interrupt register 1 (uir1) read: txd1f txd1ie resumf00000 write: resumfr tbefr rbffr txd1fr eopfr reset:00000000 $002f usb control register 1 (ucr1) read: t1seq endadd tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $0030 to $0037 usb endpoint 0 data register 0?7 (ud0r0?ud0r7) read: ue0rdx7 ue0rdx6 ue0rdx5 ue0rd x4 ue0rdx3 ue0rdx2 ue0rdx1 ue0rdx0 write: ue0tdx7 ue0tdx6 ue0tdx5 ue0tdx4 ue0tdx3 ue0tdx2 ue0tdx1 ue0tdx0 reset: indeterminate after reset $0038 to $003f usb endpoint 1/2 data register 0?7 (ud1r0?ud1r7) read: write: ue1tdx7 ue1tdx6 ue1tdx5 ue1tdx4 ue1tdx3 ue1tdx2 ue1tdx1 ue1tdx0 reset: indeterminate after reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 166 universal serial bus module (usb) motorola 13.5.1 usb address register (uadr) usben ? usb enable this read/write bit enab les/disables the usb module. when usben bit is clear, usb will not resp ond to any tokens, but still can detect usb reset signal, or eo p signals, and non-idle state if in suspend mode. reset clears this bit. after usb reset, software will set this bit to enable usb. 1 = usb module enabled 0 = usb module disabled uadd[6:0] ? usb address these bits specify the usb address of the device. reset clears these bits to $00, the default address. 13.5.2 usb interrupt register (uintr) address: $0029 bit 7654321bit 0 read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:00000000 figure 13-1. usb addr ess register (uadr) address: $002a bit 7654321bit 0 read: tbef rbff eopif rstif tbie rbie eorie rstie write: reset:00000000 = unimplemented figure 13-2. usb interr upt register (uintr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 167 tbef ? transmit buffer empty flag this flag is set after t he data stored in endpoint 0 transmit buffer has been sent and ack handshake packet is rece ived. software must clear this flag by writing a logic "1" to tbefr bit after the data is ready in the transmit buffer. this enables the next data packet transmission when endpoint 0 transmit is enabled (tx0e = 1). tbef generates an interrupt request to the cpu if the tbie bit is also set. reset clears this bit. 1 = transmit on endpoint 0 has occurred 0 = transmit on endpoint 0 has not occurred rbff ? receive buffer full flag this flag is set when the module has received one data packet and replied with ack handshake packet. soft ware must clear this flag by writing "1" to rbffr bit after a ll the received data have been read to enable the next data packet receptio n. rbff generates an interrupt request to the cpu if the rbie bit is also set. reset clears this bit. 1 = receive on endpoint 0 has occurred 0 = receive on endpoint 0 has not occurred eopif ? end of packet interrupt flag this flag is set when a valid eop signal transition is detected on the d+ and d? lines. this flag can be clear ed by writing "1" to eopifr bit. eopif generates an interr upt request to the cpu if the eopie bit is also set. reset clears this bit. 1 = end-of-packet sequen ce has been detected 0 = end-of-packet sequence has not been detected rstif ? reset interrupt flag the flag is set when a va lid reset signal state is detected on the d+ and d? lines. this flag can be cleared by writing "1" to rstifr bit. rstif generates an interr upt request to the cpu if the rstie bit is also set. reset clears this bit. 1 = usb reset condi tion has been detected 0 = usb reset condition has not been detected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 168 universal serial bus module (usb) motorola tbie ? transmit buff er interrupt enable when this bit is set, the tbef fl ag is enabled to generate an interrupt request to the cpu. when tbie is cleared, the tbef flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = tbef bit set will generat e interrupt request to cpu 0 = tbef bit set does not generate interrupt request to cpu rbie ? receive buffer interrupt enable when this bit is set, the rbff flag is enabled to generate an interrupt request to the cpu. when rbie is cleared, the rbff flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = rbff bit set will generat e interrupt request to cpu 0 = rbff bit set do es not generate inte rrupt request to cpu eopie ? end of packet interrupt enable when this bit is set, the eopif flag is enabled to generate an interrupt request to the cpu. w hen eopie is cleared, the eopif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = eopif bit set w ill generate interrup t request to cpu 0 = eopif bit set do es not generate inte rrupt request to cpu rstie ?treset interrupt enable when this bit is set, the rstif fl ag is enabled to genera te an interrupt request to the cpu. when rstie is cleared, the rstif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = rstif bit set will genera te interrupt request to cpu 0 = rstif bit set does not generate interr upt reques t to cpu note: since there are more than one interrupt flags in the register, it is possible that program use read-modify-write instruction to clear one flag, will occasionally clear the other flags wh ich was just set af ter read cycle of read-modify-write operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 169 13.5.3 usb interrupt register 1 (uir1) txd1f ? endpoint 1/2 data buffer transmit flag the flag is set after the data stor ed in endpoint 1/2 transmit buffer has been sent and a ck handshake packet from host is received. software must clear this flag by wr iting a logic 1 to txd1fr bit after the data is ready in the transmit buffer to enable the next data packet transmission when tx1e is enabl ed. reset clears this bit. 1 = transmit on endpoint 1/2 has occurred 0 = transmit on endpoint 1/2 has not occurred txd1ie ? transmit bu ffer interrupt enable when this bit is set, the txd1f flag is enabled to generate an interrupt request to the cpu. when txd1ie is cleared, the txd1f flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = txd1f bit set will gener ate interrupt request to cpu 0 = txd1f bit set does not generate interrupt request to cpu resumf ? resume flag this flag is set if the transaction from idle state to non-idle state is detected while in susp end mode (suspnd = 1). an interrupt will be generated to wake up cpu to indicate a resume signalling from host and software will clea r suspnd bit and exit from suspend mode. usb reset signals canno t be detected while in suspend mode until suspnd bit is cleared. the resumf interrupt service routine is generated by se0 to wake up th e usb module. this bit can be cleared by writing "1" to resumfr bit. reset clears this bit. 1 = usb bus activity detec ted while in suspend mode 0 = if in suspend mode, no usb bus activity has been detected address: $002e bit 7654321bit 0 read: txd1f txd1ie resumf00000 write: 0 0 resumfr tbefr rbffr txd1fr eopfr reset:00000000 figure 13-3. usb interrupt register 1 (uir1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 170 universal serial bus module (usb) motorola resumfr ? resume flag clear writing a logic "1" to th is bit clears the resumf flag. writing a "0" has no effect. reset clears this bit. 1 = writing 1 clears resumfr 0 = no effect tbefr ? transmit buff er empty flag clear writing a logic "1" to th is bit clears the tbef fl ag. writing a "0" has no effect. reset cl ears this bit. 1 = writing 1 clears tbef 0 = no effect rbffr ? receive buffer full flag clear writing a logic "1" to this bit clear s the rbff flag. wr iting a "0" has no effect. reset cl ears this bit. 1 = writing 1 clears rbff 0 = no effect txd1fr ? endpoint 1 and 2 data buffer transmit flag clear writing a logic "1" to th is bit clears the txd1f flag. writing a "0" has no effect. reset clears this bit. 1 = writing 1 clears txd1f 0 = no effect eopifr ? end of packe t interrupt flag clear writing a logic "1" to th is bit clears the eopif flag. writing a "0" has no effect. reset clears this bit. 1 = writing 1 clears eopif 0 = no effect f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 171 13.5.4 usb control register 0 (ucr0) t0seq ? endpoint 0 da ta packet pid select this bit will determine the transmit data packet pid of endpoint 0. when it is "0", the data0 pid (b0011) will be sent. when it is "1", the data1 pid (b1011) will be s ent. reset clears this bit. 1 = data1 pid will be sent on endpoint 0 0 = data0 pid will be sent on endpoint 0 stall0 ? endpoint 0 stall handshake this bit is set to genera te the stall handshake pa cket as next in or out transactions handshake packe t from endpoint 0. the usb hardware clears the sta ll0 bit when a setup pa cket is received. reset clears this bit. 1 = send stall handshake on endpoint 0 0 = do not send stall handshake on endpoint 0 tx0e ? endpoint 0 transmit enable this bit is set to ena ble data packet transmissi on from endpoint 0. software should set this bit w hen data is ready for data packet transmission. it must be cleared when no more da ta needs to be transmitted. if tx0e is "0" or tx d0f is "1", a nak handshake will be returned for the next in tok en. reset clears this bit. 1 = data is ready to be sent on endpoint 0 0 = data is not ready; respond with ack address: $002b bit 7654321bit 0 read: t0seq stall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 figure 13-4. u sb control register 0 (ucr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 172 universal serial bus module (usb) motorola rx0e ? endpoint 0 receive enable this bit is set to ena ble data packet recepti on from endpoint 0. software should set this bit when it is ready for data packet reception. it must be cleared when data cannot be received. if rx0e "0" or rbff is "1", a nak handshake will be re turned for the next out token. reset clears this bit. 1 = data is read to be received on endpoint 0 0 = not ready for data; respond with nak tp0siz[3:0] ? endpoint 0 transmit data size the tp0siz[3:0] is used to store t he number of transmit data bytes from endpoint 0. the default size of transmit data is "0" after reset. 13.5.5 usb control register 1 (ucr1) t1seq ? endpoint 1/2 da ta packet pid select this bit will determine the transmit data packet pid of endpoint 1/2. when it is "0", the data0 pid (b0011) will be sent. when it is "1", the data1 pid (b1011) will be s ent. reset clears this bit. 1 = data1 pid will be sent on endpoint 1/2 0 = data0 pid will be sent on endpoint 1/2 endadd ? endpoint address select this bit specifies the which endpoint (1 or 2) uses the eight data registers, ud1r0?u d1r7, for data transmit buffers. clearing this bit selects endpoint 1 to use the data regi sters. setting this bit selects endpoint 2 to use the data registers. address: $002f bit 7654321bit 0 read: t1seq endadd tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 figure 13-5. u sb control register 1 (ucr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 173 if all the conditions for a successf ul endpoint 2 usb response to a host?s in token are satisfied (txd1f = 0, tx1e = 1, stall2 = 0, enable2 = 1), but endpoint 1 is sele cted (endadd = 0), the module will respond with an nak handshake packet. reset clears this bit. 1 = the transmit buffer is used for endpoint 2 0 = the transmit buffer is used for endpoint 1 tx1e ? endpoint 1/2 transmit enable this bit is set to ena ble data packet transmissi on from endpoint 1/2. software should set this bit w hen data is ready for data packet transmission. it must be cleared when no more da ta needs to be transmitted. if tx1e is "0" or tx d1f is "1", a nak handshake will be returned for the next in tok en. reset clears this bit. 1 = data is ready to be sent on endpoint 1/2 0 = data is not ready; respond with ack fresum ? force resume this bit is set to force a resume st ate on usb bus lines until software clears this bit. before setting t he fresum bit, th e suspnd bit must to be cleared in order to drive t he usb bus lines. se tting the fresum bit will not cause resumf to be set. reset clears this bit. 1 = resume state forced on usb bus; only if suspnd is cleared 0 = no effect tp1siz[3:0] ? endpoint 1/ 2 transmit data size the tp1siz[3:0] is used to store t he number of transmit data bytes from endpoint 1/2. the def ault size of transmit data is "0" after reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 174 universal serial bus module (usb) motorola 13.5.6 usb control register 2 (ucr2) rstifr ? reset in terrupt flag clear writing a logic "1" to this bit clear s the rstifr flag. writing a "0" has no effect. reset clears this bit. 1 = writing 1 clears rstifr 0 = no effect tx1str ? tx1st clear writing a logic "1" to th is bit clears the tx1str flag. writing a "0" has no effect. reset clears this bit. 1 = writing 1 clears tx1str 0 = no effect pullen ? pullup enable on d? this bit is set to ena ble the internal 1.5k ? pullup resister connected between the usb d? line and 3.3v. reset clears this bit. 1 = enable 1.5k ? pullup resistor between d? and 3.3v 0 = disable 1.5k ? pullup resistor between d? and 3.3v suspnd ? usb suspend if the 3ms constant idle state is detected on the usb bus, user software should set this bit to allow the usb modul e to enter suspend mode. in the suspend mode, the cl ock to usb module will be stopped, and other unnecessary analog circuitry will be powered down. when a resume is detected (resumf = 1 ), user software must clear suspnd in the interr upt service routine. 1 = enable usb suspend mode 0 = disable usb suspend mode address: $002d bit 7654321bit 0 read: 0 0 pullen suspnd enable2 enable1 stall2 stall1 write: rstifr tx1str reset:00000000 figure 13-6. u sb control register 2 (ucr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 175 enable2 ? endpoint 2 enable this bit is set to enable endpoint 2 to respond to addressed in packet tokens. reset clears this bit. 1 = endpoint 2 enabled; and responds to in tokens 0 = endpoint 2 disabled enable1 ? endpoint 1 enable this bit is set to enable endpoint 1 to respond to addressed in packet tokens. reset clears this bit. 1 = endpoint 1 enabled; and responds to in tokens 0 = endpoint 1 disabled stall2 ? endpoint 2 stall handshake this bit is set to generate the stall handshake packet as next in transaction handshake packet from e ndpoint 2. reset clears this bit. 1 = send stall handshake on endpoint 2 0 = do not send stall handshake on endpoint 2 stall1 ? endpoint 1 stall handshake this bit is set to generate the stall handshake packet as next in transaction handshake packet from e ndpoint 1. reset clears this bit. 1 = send stall handshake on endpoint 1 0 = do not send stall handshake on endpoint 1 13.5.7 usb status register (usr) address: $002c bit 7654321bit 0 read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: reset: indeterminate after reset = unimplemented figure 13-7. usb st atus register (usr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 176 universal serial bus module (usb) motorola rseq ? received data sequence this bit indicates the type of data packet of the last received data packet on endpoint 0. rseq = 0 in dicates the last received data packet is type data0. rseq = 1 i ndicates the last received data packet is type data1. 1 = last token received on endpoi nt 0 is a data1 token 0 = last token received on endpoi nt 0 is a data0 token setup ? setup token this bit is set when the received token packet for endpoint 0 is a setup token (pid = b1101). 1 = last token received on endpoi nt 0 is a setup token 0 = last token received on endpoi nt 0 is not a setup token tx1st ? transmit first flag this bit is set if the endpoint 0 trans mit buffer empty flag (tbef) is set when the control logic is setting the endpoint 0 re ceive buffer full flag (rbff). this happens when tbef is still set at the end of an endpoint 0 reception. 1 = in transaction occurr ed before setup or out 0 = in transaction occurr ed after setup or out rpsiz[3:0] ? received data size the rpsiz[3:0] indicates the number of received data bytes in a data packet. reset will not affect these bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola universal serial bus module (usb) 177 13.5.8 usb endpoint 0 data registers 0 to 7 (ud0r0?ud0r7) ue0rdx[7:0] ? endpoint 0 receive data buffers these eight 8-bit buffers are seri ally loaded with out token or setup token data rece ived over the usb?s d+ and d? lines. these buffers are for endpoint 0. ue0tdx[7:0] ? endpoint 0 transmit data buffers these eight 8-bit buffers are loaded by user software with data to be sent on the usb bus on the next in token di rected at endpoint 0. 13.5.9 usb endpoint 1/2 data registers 0 to 7 (ud1r0?ud1r7) ue1tdx[7:0] ? endpoint 1/ 2 transmit data buffers these eight 8-bit buffers are loaded by user software with data to be sent on the usb bus on the next in token direct ed at endpoint 1 or endpoint 2. the endadd bit in the usb control register 1 determines either endpoint 1 or endpoint 2 uses these buffers. address: $0030?$0037 bit 7654321bit 0 read: ue0rdx7 ue0rdx6 ue0rdx5 ue0rd x4 ue0rdx3 ue0rdx2 ue0rdx1 ue0rdx0 write: ue0tdx7 ue0tdx6 ue0tdx5 ue0tdx4 ue0tdx3 ue0tdx2 ue0tdx1 ue0tdx0 reset: indeterminate after reset figure 13-8. usb endpoint 0 data registers 0 to 7 (ud0r0?ud0r7) address: $0038?$003f bit 7654321bit 0 read: write: ue1tdx7 ue1tdx6 ue1tdx5 ue1tdx4 ue1tdx ue1tdx2 ue1tdx1 ue1tdx0 reset: indeterminate after reset figure 13-9. usb endpoint 1 data registers 0 to 7 (ud1r0?ud1r7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC908BD48 ? rev. 2.0 178 universal serial bus module (usb) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola multi-master iic interface (mmiic) 179 data sheet ? mc68HC908BD48 section 14. multi-master iic interface (mmiic) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.5 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 14.5.1 multi-master iic address regist er (mmadr) . . . . . . . . . . 182 14.5.2 multi-master iic control register (mmcr) . . . . . . . . . . . . 183 14.5.3 multi-master iic ma ster control register (mimcr) . . . . . . 184 14.5.4 multi-master iic stat us register (mmsr) . . . . . . . . . . . . . 186 14.5.5 multi-master iic data transm it register (mmdtr) . . . . . . 188 14.5.6 multi-master iic data receiv e register (mmdrr ) . . . . . . 189 14.6 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 190 14.2 introduction this multi-master iic (mmi ic) interface is designe d for internal serial communication between the mcu and other iic devices. a hardware circuit generates "start" and "stop" signal, while byte by byte data transfer is interrupt driven by the so ftware algorithm. therefore, it can greatly help the software in dealin g with other devices to have higher system efficiency in a typi cal digital monitor system. this module not only can be applied in internal co mmunications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. it also prov ides the flexib ility of hooking additional devices to an existing sys tem for future expansion without adding extra hardware. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) data sheet mc68HC908BD48 ? rev. 2.0 180 multi-master iic interface (mmiic) motorola this multi-master iic module uses t he iicscl clock lin e and the iicsda data line to communicate wi th external ddc host or iic interface. these two pins are shared with port pins ptd5 and ptd6 respectively. the outputs of iicsda and ii cscl pins are open-dr ain type ? no clamping diode is connected betwe en the pin and internal v dd . the maximum data rate typically is 750k-bps. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pf. 14.3 features compatibility with multi-master iic bus standard software controllable a cknowledge bit generation interrupt driven byte by byte data transfer calling address iden tification interrupt auto detection of r/w bit and switching of transmit or receive mode detection of start, repeat ed start, and stop signals auto generation of start and stop condition in master mode arbitration loss detection and no -ack awareness in master mode 8 selectable baud ra te master clocks automatic recognition of th e received acknowledge bit 14.4 i/o pins the mmiic module uses two i/o pins , shared with standard port i/o pins. the full name of the mmiic i/o pins are listed in table 14-1 . the generic pin name appear in the text that follows. table 14-1. pin name conventions mmiic generic pin names: full mcu pin names: pin selected for iic function by: sda ptd6/iicsda iicdate bit in pdcr ($0049) scl ptd5/iicscl iicscle bit in pdcr ($0049) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola multi-master iic interface (mmiic) 181 14.5 registers six registers are associ ated with the multi-master iic module, they are outlined in the following sections. table 14-2. mmiic i/ o register summary addr.register name bit 7654321bit 0 $004a multi-master iic master control register (mimcr) read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: reset:00000000 $004b multi-master iic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $004c multi-master iic control register (mmcr) read: mmen mmien 00 mmtxak 000 write: reset:00000000 $004d multi-master iic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 $004e multi-master iic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 $004f multi-master iic data receive register (mmdrr) read: mmrd7 mmrd6 mmrd5 mmr d4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) data sheet mc68HC908BD48 ? rev. 2.0 182 multi-master iic interface (mmiic) motorola 14.5.1 multi-master iic address register (mmadr) mmad[7:1] ? multi-master address these 7 bits can be the mmiic interf ace?s own specific slave address in slave mode or the ca lling address when in ma ster mode. reset sets a default value of $a0. mmextad ? multi-mast er expanded address this bit is set to expa nd the calling address of the mmiic in slave mode. when set, the mmiic will acknowledge the general call address $00 and the ma tched 4-bit msb address, mmad[7:4]. for example, when mmad[7:1] = $a1 and mmextad = 1, the mmiic calling address is $a0, and it wi ll acknowledge calling addresses $00 and $a0 to $af. reset clears this bit. 1 = mmiic calling address is $mmad[7:4]0 mmiic respond address is $0 0, and $mmad[7:4]0 to $mmad[7:4]f 0 = mmiic address is $mmad[7:1] address: $004b bit 7654321bit 0 read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 figure 14-1. multi- master iic address register (mmadr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola multi-master iic interface (mmiic) 183 14.5.2 multi-master iic control register (mmcr) mmen ? multi-master iic enable this bit is set to enable the multi-mast er iic module. when mmen = 0, module is disabled and all flags will restor e to its power- on default states. reset clears this bit. 1 = mmiic module enabled 0 = mmiic module disabled mmien ? multi-master iic interrupt enable when this bit is set, the mmtx if, mmrxif, mmalif, and mmnakif flags are enabled to generate an in terrupt request to the cpu. when mmien is cleared, the these flags are prevented from generating an interrupt request. re set clears this bit. 1 = mmtxif, mmrxif, mmalif, and/or mmnakif bit set will generate interrupt request to cpu 0 = mmtxif, mmrxif, mmalif, a nd/or mmnakif bit set will not generate interrupt request to cpu mmtxak ? transmit acknowledge enable this bit is set to disable the mmiic from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. when mmtxak is cleared, an acknowledge signal wi ll be sent at the 9th clock bit. reset clears this bit. 1 = mmiic does not send ackno wledge signals at 9th clock bit 0 = mmiic sends acknowledge signal at 9th clock bit address: $004c bit 7654321bit 0 read: mmen mmien 00 mmtxak 000 write: reset:00000000 = unimplemented figure 14-2. multi-master iic control register (mmcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) data sheet mc68HC908BD48 ? rev. 2.0 184 multi-master iic interface (mmiic) motorola 14.5.3 multi-master iic master control register (mimcr) mmalif ? multi-master arbi tration lost interrupt flag this flag is set when software atte mpt to set mmast but the mmbb has been set by detecting the start condition on the lin es or when the mmiic is transmitting a "1" to sd a line but detecte d a "0" from sda line in master mode ? an arbitration loss. this bit generates an interrupt request to the cpu if th e mmien bit in mmcr is also set. this bit is cleared by writi ng "0" to it or by reset. 1 = lost arbitrati on in master mode 0 = no arbitration lost mmnakif ? no acknowledge interrupt flag this flag is only set in master mode (mmast = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. this flag also clear s mmast. mmnakif generates an interrupt request to cpu if the mmie n bit in mmcr is also set. this bit is cleared by writing "0" to it or by reset. 1 = no acknowl edge bit detected 0 = acknowledg e bit detected mmbb ? bus busy flag this flag is set after a start conditi on is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the mmiic is disabled. reset clears this bit. 1 = start condition detected 0 = stop condition detected or mmiic is disabled address: $004a bit 7654321bit 0 read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: reset:00000000 figure 14-3. multi-master iic ma ster control register (mimcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola multi-master iic interface (mmiic) 185 mmast ? master control bit this bit is set to initia te a master mode transf er. in master mode, the module generates a star t condition to the sda and scl lines, followed by sending the calli ng address stored in mmadr. when the mmast bit is cleared by mmnakif set (no acknowledge) or by software, the mo dule generates the stop condition to the lines after the current byte is transmitted. if an arbitration loss occurs (mmali f = 1), the module reverts to slave mode by clearing mmast, and releasing sda and scl lines immediately. this bit is cleared by writi ng "0" to it or by reset. 1 = master mode operation 0 = slave mode operation mmrw ? master read/write this bit will be tr ansmitted out as bit 0 of th e calling address when the module sets the mmast bit to ent er master mode. the mmrw bit determines the transfer direction of the data bytes that follows. when it is "1", the module is in master receive mode. when it is "0", the module is in master transmit mode. reset clears this bit. 1 = master mode receive 0 = master mode transmit mmbr2?mmbr0 ? baud rate select these three bits select one of eigh t clock rates as the master clock when the module is in master mode. since this master clock is deri ved the cpu bus cl ock, the user program should not execute the wa it instruction when the mmiic module in master mode. this will cause the sda and scl lines to hang, as the wait instru ction places the mcu in wait mode, with cpu clock is halted. these bits are cleared upon reset. (see table 14-3 . baud rate select .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) data sheet mc68HC908BD48 ? rev. 2.0 186 multi-master iic interface (mmiic) motorola 14.5.4 multi-master iic status register (mmsr) mmrxif ? multi-master ii c receive interrupt flag this flag is set after the data receiv e register (mmdrr) is loaded with a new received data. once the mm drr is loaded with received data, no more received data can be loaded to the mmdrr register until the cpu reads the data from the mmdrr to clear mmrxbf flag. mmrxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or by reset; or when the mmen = 0. 1 = new data in data re ceive register (mmdrr) 0 = no data received table 14-3. baud rate select mmbr2 mmbr1 mmbr0 baud rate 000 750k 001 375k 0 1 0 187.5k 011 93.75k 100 46.875k 101 23.437k 110 11.719k 1 1 1 5.859k note: cpu bus clock is external clock 4 = 6mhz address: $004d bit 7654321bit 0 read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 = unimplemented figure 14-4. multi-master ii c status register (mmsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola multi-master iic interface (mmiic) 187 mmtxif ? multi-master transmit interrupt flag this flag is set when data in the data transmit regi ster (mmdtr) is downloaded to the output circuit, and that new data ca n be written to the mmdtr. mmtxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or when the mmen = 0. 1 = data transfer completed 0 = data transfer in progress mmatch ? multi-master address match this flag is set when the received data in the data receive register (mmdrr) is an calling address whic h matches with the address or its extended addresses (mmextad=1) specified in the mmadr register. 1 = received address matches mmadr 0 = received address does not match mmsrw ? multi-master slave read/write this bit indicates the data direction when the module is in slave mode. it is updated after t he calling address is rece ived from a master device. mmsrw = 1 when the calling ma ster is reading data from the module (slave transmit mode). mmsrw = 0 when the master is writing data to the m odule (receive mode). 1 = slave mode transmit 0 = slave mode receive mmrxak ? multi-master receive acknowledge when this bit is clear ed, it indicate s an acknowledge signal has been received after the comp letion of 8 data bits transmission on the bus. when mmrxak is set, it indicates no acknow ledge signal has been detected at the 9th clo ck; the module will releas e the sda line for the master to generate "stop" or "repeated start" condi tion. reset sets this bit. 1 = no acknowledge signal received at 9th clock bit 0 = acknowledge signal re ceived at 9th clock bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) data sheet mc68HC908BD48 ? rev. 2.0 188 multi-master iic interface (mmiic) motorola mmtxbe ? multi-master transmit buffer empty this flag indicates the status of th e data transmit r egister (mmdtr). when the cpu writes the data to the mmdtr, the mmtxbe flag will be cleared. mmtxbe is se t when mmdtr is empt ied by a transfer of its data to the out put circuit. reset sets this bit. 1 = data transmit register empty 0 = data transmit register full mmrxbf ? multi-master receive buffer full this flag indicates the status of th e data receive register (mmdrr). when the cpu reads the data from the mmdrr, the mmrxbf flag will be cleared. mmrx bf is set when mmdrr is full by a transfer of data from the input circ uit to the mmdrr. re set clears this bit. 1 = data receive register full 0 = data receive register empty 14.5.5 multi-master iic data transmit register (mmdtr) when the mmiic module is enabled, mmen = 1, data written into this register depends on whether module is in master or slave mode. in slave mode, the data in mmdtr will be transferr ed to the out put circuit when: the module detects a matched calling addres s (mmatch = 1), with the calling master requesting data (mmsrw = 1); or the previous data in the output circuit has be tr ansmitted and the receiving master returns an a cknowledge bit, indicated by a received acknowl edge bit (mmrxak = 0). address: $004e bit 7654321bit 0 read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 figure 14-5. multi-master iic da ta transmit register (mmdtr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) registers mc68HC908BD48 ? rev. 2.0 data sheet motorola multi-master iic interface (mmiic) 189 if the calling master does not re turn an acknowledge bit (mmrxak = 1), the module will release the sda line for master to generate a "stop" or "repeated start" condition. the data in the mmdtr will not be transferred to the output circuit until the nex t calling from a master. the transmit buffer empty flag remains cleared (mmtxbe = 0). in master mode, the dat a in mmdtr will be tr ansferred to the output circuit when: the module receives an acknow ledge bit (mmr xak = 0), after setting master transmit m ode (mmrw = 0), and the calling address has been transmitted; or the previous data in the output circuit has be tr ansmitted and the receiving slave retu rns an acknowledge bi t, indicated by a received acknowl edge bit (mmrxak = 0). if the slave does not return an acknowledge bit (mmrxak = 1), the master will gener ate a "stop" or "repeated start" condition. th e data in the mmdtr will not be trans ferred to the output circuit. the transmit buffer empty flag remains cleared (mmtxbe = 0). the sequence of events for slave tr ansmit and master transmit are illustrated in figure 14-7 . 14.5.6 multi-master iic data receive register (mmdrr) when the mmiic module is enabled, mmen = 1, data in this read-only register depends on whether module is in master or slave mode. in slave mode, t he data in mmdrr is: address: $004f bit 7654321bit 0 read: mmrd7 mmrd6 mmrd5 mmr d4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 = unimplemented figure 14-6. multi-master iic data receive r egister (mmdrr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) data sheet mc68HC908BD48 ? rev. 2.0 190 multi-master iic interface (mmiic) motorola the calling address from the ma ster when the address match flag is set (mmatch = 1); or the last data received when mmatch = 0. in master mode, the data in the mmdrr is: the last data received. when the mmdrr is read by the cpu, the receive buffer full flag is cleared (mmrxbf = 0), and the next re ceived data is loaded to the mmdrr. each time when new data is loaded to the mmdrr, the mmrxif interrupt flag is set, indicati ng that new data is available in mmdrr. the sequence of events for slave receive and master receive are illustrated in figure 14-7 . 14.6 programming considerations when the mmiic module detects an arbi tration loss in ma ster mode, it will release both sda and scl lines im mediately. but if there are no further stop condi tions detected, the module will hang up. therefore, it is recommended to have time-out soft ware to recover from such ill condition. the software can start the ti me-out counter by looking at the mmbb (bus busy) flag in the mimcr and rese t the counter on the completion of one byte tr ansmission. if a time-out occur, software can clear the mmen bit (disable mmiic module) to rele ase the bus, and hence clearing the mm bb flag. this is the onl y way to clear the mmbb flag by software if the module hangs up due to a no stop condition received. the mmiic c an resume operation again by setting the mmen bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) programming considerations mc68HC908BD48 ? rev. 2.0 data sheet motorola multi-master iic interface (mmiic) 191 figure 14-7. data transf er sequences for master/sla ve transmit/receive modes start address ack tx data1 mmtxbe=0 mmrw=0 mmast=1 mmtxif=1 mmtxbe=1 mmnakif=1 mmast=0 mmtxbe=1 (a) master transmit mode (b) master receive mode (c) slave transmit mode mmtxif=1 mmtxbe=0 ack tx datan nak stop mmtxif=1 mmtxbe=1 start address ack rx data1 mmrxbf=0 mmast=1 mmtxbe=0 mmrxbf=1 mmrxif=1 mmnakif=1 mmast=0 mmrxif=1 mmrxbf=1 ack rx datan nak stop 1 start address ack tx data1 mmtxbe=1 mmrxbf=0 mmnakif=1 mmtxbe=0 mmtxbe=1 (d) slave receive mode mmtxif=1 ack tx datan nak stop mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=1 mmtxif=1 mmtxbe=1 0 start address ack rx data1 mmrxbf=1 mmrxif=1 mmrxif=1 mmrxbf=1 ack rx datan nak stop mmtxbe=0 mmrxbf=0 mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=0 data1 mmdrr datan mmdrr data1 mmdtr data2 mmdtr datan+2 mmdtr data1 mmdtr data2 mmdtr data3 mmdtr datan+2 mmdtr (dummy data mmdtr) mmrw=1 data1 mmdrr datan mmdrr 0 1 key: shaded data packets indicate a transmit by the mcu?s mmiic module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . multi-master iic interface (mmiic) data sheet mc68HC908BD48 ? rev. 2.0 192 multi-master iic interface (mmiic) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 193 data sheet ? mc68HC908BD48 section 15. ddc12ab interface 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.5 ddc protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.6 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 15.6.1 ddc address register (dadr) . . . . . . . . . . . . . . . . . . . . . 196 15.6.2 ddc2 address register (d2adr) . . . . . . . . . . . . . . . . . . . 197 15.6.3 ddc control register (dcr) . . . . . . . . . . . . . . . . . . . . . . . 198 15.6.4 ddc master control register (d mcr) . . . . . . . . . . . . . . . 199 15.6.5 ddc status register (dsr) . . . . . . . . . . . . . . . . . . . . . . . . 202 15.6.6 ddc data transmit r egister (ddtr) . . . . . . . . . . . . . . . . 204 15.6.7 ddc data receive register (ddrr) . . . . . . . . . . . . . . . . . 205 15.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 206 15.2 introduction this ddc12ab interface module is used by the digital monitor to show its identification informat ion to the video contro ller. it contains ddc1 hardware and a two-wire, bidirectional serial bus which is fully compatible with multi-master ii c bus protocol to support ddc2ab interface. this module not only can be applied in internal co mmunications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. it also prov ides the flexib ility of hooking additional devices to an existing sys tem for future expansion without adding extra hardware. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 194 ddc12ab interface motorola this ddc12ab module uses the ddcscl clock li ne and the ddcsda data line to communicate wi th external ddc host or iic interface. these two pins are shared with port pins ptd3 and ptd2 respectively. the outputs of ddcsda and ddcscl pins are open-drain type ? no clamping diode is connected bet ween the pin and internal v dd . the maximum data rate typically is 100 k-bps. the maximum communication length and the number of devices that can be c onnected are limited by a maximum bus capa citance of 400pf. 15.3 features ddc1 hardware compatibility with multi-master iic bus standard software controllable a cknowledge bit generation interrupt driven byte by byte data transfer calling address iden tification interrupt auto detection of r/w bit and switching of transmit or receive mode detection of start, repeat ed start, and stop signals auto generation of start and stop condition in master mode arbitration loss detection and no -ack awareness in master mode 8 selectable baud ra te master clocks automatic recognition of th e received acknowledge bit 15.4 i/o pins the ddc12ab module uses two i/o pi ns, shared with standard port i/o pins. the full name of the ddc 12ab i/o pins are listed in table 15-1 . the generic pin name appear in the text that follows. table 15-1. pin name conventions ddc12ab generic pin names: full mcu pin names: pin selected for ddc function by: sda ptd2/ddcsda ddcdate bit in pdcr ($0049) scl ptd3/ddcscl ddcscle bit in pdcr ($0049) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface i/o pins mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 195 table 15-2. ddc i/o register summary addr.register name bit 7654321bit 0 $0016 ddc master control register (dmcr) read: alif nakif bb mast mrw br2 br1 br0 write: reset:00000000 $0017 ddc address register (dadr) read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 $0018 ddc control register (dcr) read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 $0019 ddc status register (dsr) read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 $001a ddc data transmit register (ddtr) read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 $001b ddc data receive register (ddrr) read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 $001c ddc2 address register (d2adr) read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 196 ddc12ab interface motorola 15.5 ddc protocols in ddc1 protocol comm unication, the module is in transmit mode. the data written to the transmi t register is continuou sly clocked out to the sda line by the rising edge of th e vsync input si gnal. during ddc1 communication, a falling transition on the sc l line can be detected to generate an interrupt to t he cpu for mode switching. in ddc2ab protocol co mmunication, the modu le can be either in transmit mode or in rece ive mode, contro lled by the calling master. in ddc2 protocol comm unication, the module wil l act as a standard iic module, able to act as a master or a slave device. 15.6 registers seven registers are associated with the ddc module, t hey outlined in the following sections. 15.6.1 ddc address register (dadr) dad[7:1] ? ddc address these 7 bits can be the ddc2 interf ace?s own specif ic slave address in slave mode or the ca lling address when in ma ster mode. reset sets a default value of $a0. address: $0017 bit 7654321bit 0 read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 figure 15-1. ddc addr ess register (dadr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface registers mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 197 extad ? ddc expanded address this bit is set to expand the calling address of t he ddc in slave mode. when set, the ddc w ill acknowledge the gene ral call address $00 and the matched 4-bit msb address, dad[7:4]. for example, when dad[ 7:1] = $a1 and extad = 1, the ddc calling address is $a0, and it will a cknowledge calling addresses $00 and $a0 to $af. reset clears this bit. 1 = ddc calling addre ss is $dad[7:4]0 ddc respond address is $00, and $dad[7:4]0 to $dad[7:4]f 0 = ddc addre ss id $dad[7:1] 15.6.2 ddc2 address register (d2adr) d2ad[7:1] ? ddc2 address these 7 bits represent the sec ond slave address for the ddc2bi protocol. d2ad[7:1] shoul d be set to the same value as dad[7:1] in dadr if user application do not use ddc2bi. reset clears all bits this register. address: $001c bit 7654321bit 0 read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 figure 15-2. ddc2 addr ess register (d2adr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 198 ddc12ab interface motorola 15.6.3 ddc control register (dcr) den ? ddc enable this bit is set to ena ble the ddc module. w hen den = 0, module is disabled and all flags will restore to its power-o n default states. reset clears this bit. 1 = ddc module enabled 0 = ddc module disabled dien ? ddc interrupt enable when this bit is set, the txif, rxif, alif, and nakif flags are enabled to generate an inte rrupt request to the cpu. when dien is cleared, the these flag s are prevented from generating an interrupt request. reset clears this bit. 1 = txif, rxif, alif, and/or naki f bit set will generate interrupt request to cpu 0 = txif, rxif, alif, and/or n akif bit set will not generate interrupt request to cpu txak ? transmit a cknowledge enable this bit is set to dis able the ddc from sendi ng out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. when txak is cleared, an acknowledge si gnal will be sent at the 9th clock bit. reset clears this bit. 1 = ddc does not send acknowl edge signals at 9th clock bit 0 = ddc sends ac knowledge signal at 9th clock bit address: $0018 bit 7654321bit 0 read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 = unimplemented figure 15-3. ddc cont rol register (dcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface registers mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 199 sclien ? scl interrupt enable when this bit is set, the sclif flag is enabled to generate an interrupt request to the cpu. when sclien is cleared, sclif is prevented from generating an interrupt request. reset clears this bit. 1 = sclif bit set will genera te interrupt request to cpu 0 = sclif bit set wi ll not generate interr upt request to cpu ddc1en ? ddc1 pr otocol enable this bit is set to ena ble ddc1 protocol. the ddc 1 protocol will use the vsync input (from sync processor) as the master clock input to the ddc module. vsync risi ng-edge will c ontinuously clock out the data to the output circuit. no calli ng address comparison is performed. the srw bit in ddc status register (dsr) will always read as "1". reset clears this bit. 1 = ddc1 protocol enabled 0 = ddc1 protocol disabled 15.6.4 ddc master control register (dmcr) alif ? ddc arbitratio n lost interrupt flag this flag is set when software atte mpt to set mast but the bb has been set by detecting the st art condition on the lines or when the ddc is transmitting a "1" to sda line but detected a "0" from sda line in master mode ? an ar bitration loss. this bi t generates an interrupt request to the cpu if the dien bit in dcr is also set. this bit is cleared by writing "0" to it or by reset. 1 = lost arbitrati on in master mode 0 = no arbitration lost address: $0016 bit 7654321bit 0 read: alif nakif bb mast mrw br2 br1 br0 write: reset:00000000 figure 15-4. ddc master control register (dmcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 200 ddc12ab interface motorola nakif ? no acknowledge interrupt flag this flag is only set in master mo de (mast = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. this flag also clears mast. nakif generat es an interrupt request to cpu if t he dien bit in dcr is also set. this bit is cleared by writing "0" to it or by reset. 1 = no acknowl edge bit detected 0 = acknowledg e bit detected bb ? bus busy flag this flag is set after a start conditi on is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the ddc is disabled. reset clears this bit. 1 = start condition detected 0 = stop condition detect ed or ddc is disabled mast ? master control bit this bit is set to initia te a master mode transf er. in master mode, the module generates a star t condition to the sda and scl lines, followed by sending the calli ng address stored in dadr. when the mast bit is cleared by nakif set (no acknowledge) or by software, the module generat es the stop conditi on to the lines after the current byte is transmitted. if an arbitration loss occurs (alif = 1), the module reverts to slave mode by clearing mast, and releasing sda and scl lines immediately. this bit is cleared by writi ng "0" to it or by reset. 1 = master mode operation 0 = slave mode operation mrw ? master read/write this bit will be tr ansmitted out as bit 0 of th e calling address when the module sets the mast bit to enter master mode. the mrw bit determines the transfer direction of the data bytes that follows. when it is "1", the module is in master receive mode. when it is "0", the module is in master transmit mode. reset clears this bit. 1 = master mode receive 0 = master mode transmit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface registers mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 201 br2?br0 ? baud rate select these three bits select one of eigh t clock rates as the master clock when the module is in master mode. since this master clock is deri ved the cpu bus cl ock, the user program should not execute the wait instruction when the ddc module in master mode. this will cause the sda and scl lines to hang, as the wait instru ction places the mcu in wait mode, with cpu clock is halted. these bits are cleared upon reset. (see table 15-3 . baud rate select .) table 15-3. baud rate select br2 br1 br0 baud rate 000 100k 001 50k 010 25k 011 12.5k 1 0 0 6.25k 1 0 1 3.125k 1 1 0 1.56k 1 1 1 0.78k note: cpu bus clock is external clock 4 = 6mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 202 ddc12ab interface motorola 15.6.5 ddc status register (dsr) rxif ? ddc receive interrupt flag this flag is set after t he data receive register (ddrr) is loaded with a new received data. once the ddrr is loaded with received data, no more received data can be loaded to the ddrr register until the cpu reads the data from t he ddrr to clear rxbf fl ag. rxif generates an interrupt request to cpu if the dien bi t in dcr is also set. this bit is cleared by writing "0" to it or by reset; or when the den = 0. 1 = new data in data re ceive register (ddrr) 0 = no data received txif ? ddc transmit interrupt flag this flag is set when data in the data transmit register (ddtr) is downloaded to the output circuit, and that new data ca n be written to the ddtr. txif generates an interrup t request to cpu if the dien bit in dcr is also set. this bit is clea red by writing "0" to it or when the den = 0. 1 = data transfer completed 0 = data transfer in progress match ? ddc address match this flag is set when the received data in the data receive register (ddrr) is an calling address which ma tches with the address or its extended addresses (extad=1) specif ied in the d adr register. 1 = received address matches dadr 0 = received address does not match address: $0019 bit 7654321bit 0 read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 = unimplemented figure 15-5. ddc status register (dsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface registers mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 203 srw ? ddc slav e read/write this bit indicates the data direction when the module is in slave mode. it is updated after t he calling address is rece ived from a master device. srw = 1 when the calling mast er is reading data from the module (slave transmit mode). srw = 0 when the master is writing data to the module (receive mode). 1 = slave mode transmit 0 = slave mode receive rxak ? ddc receive acknowledge when this bit is clear ed, it indicate s an acknowledge signal has been received after the comp letion of 8 data bits transmission on the bus. when rxak is set, it indicates no acknowledge signal has been detected at the 9th clo ck; the module will releas e the sda line for the master to generate "stop" or "repeated start" condi tion. reset sets this bit. 1 = no acknowledge signal received at 9th clock bit 0 = acknowledge signal re ceived at 9th clock bit sclif ? scl interrupt flag this flag is set when a falling edge is detected on the scl line, only if ddc1en bit is set. scli f generates an interrupt request to cpu if the sclien bit in dcr is al so set. sclif is cleared by writing "0" to it or when the dcc1en = 0, or den = 0. reset clears this bit. 1 = falling edge de tected on scl line 0 = no falling edge detected on scl line txbe ? ddc transmit buffer empty this flag indicates the status of th e data transmit r egister (ddtr). when the cpu writes the data to the ddtr, the t xbe flag will be cleared. txbe is set when ddtr is em ptied by a transf er of its data to the output circuit. reset sets this bit. 1 = data transmit register empty 0 = data transmit register full f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 204 ddc12ab interface motorola rxbf ? ddc rece ive buffer full this flag indicates the status of th e data receive register (ddrr). when the cpu reads the data from the ddrr, t he rxbf flag will be cleared. rxbf is set when ddrr is full by a transfer of data from the input circuit to the ddrr. reset clears this bit. 1 = data receive register full 0 = data receive register empty 15.6.6 ddc data transmit register (ddtr) when the ddc module is enabled, den = 1, data written into this register depends on whether module is in master or slave mode. in slave mode, the data in ddtr will be transferre d to the output circuit when: the module detects a matched ca lling address (match = 1), with the calling master re questing data (srw = 1); or the previous data in the output circuit has be tr ansmitted and the receiving master returns an a cknowledge bit, indicated by a received acknowledge bit (rxak = 0). if the calling master does not return an acknowledge bit (rxak = 1), the module will release the sda line for master to generate a "stop" or "repeated start" condition. the data in the ddtr will not be transferred to the output circuit until the nex t calling from a master. the transmit buffer empty flag remains cleared (txbe = 0). in master mode, the data in ddtr will be transfe rred to the output circuit when: address: $001a bit 7654321bit 0 read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 figure 15-6. ddc data tr ansmit register (ddtr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface registers mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 205 the module receives an ack nowledge bit (r xak = 0), after setting master transmit mode (m rw = 0), and the calling address has been transmitted; or the previous data in the output circuit has be tr ansmitted and the receiving slave retu rns an acknowledge bi t, indicated by a received acknowledge bit (rxak = 0). if the slave does not return an a cknowledge bit (rxak = 1), the master will generate a "stop" or "repeated start" condition. the data in the ddtr will not be transferred to the output circuit. the transmit buffer empty flag remains cleared (txbe = 0). the sequence of events for slave tr ansmit and master transmit are illustrated in figure 15-8 . 15.6.7 ddc data receive register (ddrr) when the ddc module is enabled, den = 1, data in this read-only register depends on whether module is in master or slave mode. in slave mode, the data in ddrr is: the calling address from the ma ster when the address match flag is set (match = 1); or the last data received when match = 0. in master mode, the data in the ddrr is: the last data received. address: $001b bit 7654321bit 0 read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 = unimplemented figure 15-7. ddc data re ceive register (ddrr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 206 ddc12ab interface motorola when the ddrr is read by the cpu, the receive buf fer full flag is cleared (rxbf = 0), and the next received data is loade d to the ddrr. each time when new data is loaded to the d drr, the rxif interrupt flag is set, indicating that new data is available in ddrr. the sequence of events for slave receive and master receive are illustrated in figure 15-8 . 15.7 programming considerations when the ddc module detect s an arbitration loss in master mode, it will release both sda and scl lines immediately. but if there are no further stop conditions detected, the module will hang up. therefore, it is recommended to have time -out software to re cover from such ill condition. the software can start the ti me-out counter by looking at the bb (bus busy) flag in th e dmcr and reset the c ounter on the completion of one byte transmission. if a time-out occur, software can clear the den bit (disable ddc module) to releas e the bus, and hence clearing the bb flag. this is the only way to clear the bb flag by software if the module hangs up due to a no stop condition received. the ddc can resume operation again by se tting the den bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface programming considerations mc68HC908BD48 ? rev. 2.0 data sheet motorola ddc12ab interface 207 figure 15-8. data transf er sequences for master/sla ve transmit/receive modes start address ack tx data1 txbe=0 mrw=0 mast=1 txif=1 txbe=1 nakif=1 mast=0 txbe=1 (a) master transmit mode (b) master receive mode (c) slave transmit mode txif=1 txbe=0 ack tx datan nak stop txif=1 txbe=1 start address ack rx data1 rxbf=0 mast=1 txbe=0 rxbf=1 rxif=1 nakif=1 mast=0 rxif=1 rxbf=1 ack rx datan nak stop 1 start address ack tx data1 txbe=1 rxbf=0 nakif=1 txbe=0 txbe=1 (d) slave receive mode txif=1 ack tx datan nak stop rxbf=1 rxif=1 match=1 srw=1 txif=1 txbe=1 0 start address ack rx data1 rxbf=1 rxif=1 rxif=1 rxbf=1 ack rx datan nak stop txbe=0 rxbf=0 rxbf=1 rxif=1 match=1 srw=0 data1 ddrr datan ddrr data1 ddtr data2 ddtr datan+2 ddtr data1 ddtr data2 ddtr data3 ddtr datan+2 ddtr (dummy data ddtr) mrw=1 data1 ddrr datan ddrr 0 1 key: shaded data packets indicate a transmit by the mcu?s ddc module f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ddc12ab interface data sheet mc68HC908BD48 ? rev. 2.0 208 ddc12ab interface motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 209 data sheet ? mc68HC908BD48 section 16. sync processor 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.5.1 polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.1.1 hsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.1.2 vsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.1.3 composite sync polarity detect ion . . . . . . . . . . . . . . . . 214 16.5.2 sync signal counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.5.3 polarity controll ed hsynco and vsynco outputs. . . . . 215 16.5.4 clamp pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.5 low vertical frequency detect . . . . . . . . . . . . . . . . . . . . . 217 16.6 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 16.6.1 sync processor control & stat us register ( spcsr). . . . . 217 16.6.2 sync processor input/output control register (spiocr) . 219 16.6.3 vertical frequency registers (vfrs) . . . . . . . . . . . . . . . . . 221 16.6.4 hsync frequency registers (hfrs). . . . . . . . . . . . . . . . . . 223 16.6.5 sync processor control register 1 (spcr1). . . . . . . . . . . 225 16.6.6 h&v sync output control regi ster (hvocr) . . . . . . . . . . 226 16.7 system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 16.2 introduction the sync processor is designed to detect and process sync signals inside a digital monitor system ? from separated hsync and vsync inputs, or from composite sync in puts such as sync -on-green (sog). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 210 sync processor motorola after detection and the necessary po larity correction and/or sync separation, the correct ed sync signals are sent out. the mcu can also send commands to other m onitor circuitry, such as for the geometry correction and osd, using the ddc12a b and/or the iic communication channels. the block diagram of the sync processor is shown in figure 16-1 . note: all quoted timings in this section assume an internal bus frequency of 6mhz. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor features mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 211 16.3 features features of the sync proc essor include the following: polarity detector horizontal frequency counter vertical frequency counter low vertical frequency indicator (40.7hz) polarity controlled hsynco and vsynco outputs: ? from separate hsync and vsync ? from composite sync on hsync or sog input pin ? from internal selectable fr ee running hsync and vsync pulses clamp pulse output to the external pre-amp chip internal schmitt trigger on hsy nc, vsync, and so g input pins to improve noise immunity 16.4 i/o pins the sync processor uses six i/o pins, with four pins shared with standard port i/o pins. the full name of the sync processor i/o pins are listed in table 16-1 . the generic pin name app ear in the text that follows. table 16-1. pin name conventions sync processor generic pin names: full mcu pin names: pin selected for sync processor function by: hsync hsync ? vsync vsync ? sog pte0/sog/tch0 soge bit in config1 ($001d) hsynco pte1/hsynco hsyncoe bit in config 1 ($001d) vsynco pte2/vsynco vsyncoe bit in config 1 ($001d) clamp ptd4/clamp clampe bit in pdcr ($0049) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 212 sync processor motorola table 16-2. sync processor i/o register summary addr.register name bit 7654321bit 0 $0040 sync processor control and status register (spcsr) read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 $0041 vertical frequency high register (vfhr) read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 $0042 vertical frequency low register (vflr) read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 $0043 hsync frequency high register (hfhr) read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 $0044 hsync frequency low register (hflr) read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 $0045 sync processor i/o control register (spiocr) read: vsyncs hsyncs coinv r sogsel clampoe bpor sout write: reset:00000000 $0046 sync processor control register 1 (spcr1) read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:00000000 $0047 h&v sync output control register (hvocr) read: r 0000 hvocr2 hvocr1 hvocr0 write: reset:00000000 = unimplemented r = reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor functional blocks mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 213 16.5 functional blocks figure 16-1. sync pr ocessor block diagram 13-bit counter 48 a 1 b s extracted vsync a 1 b s svf comp sout vinvo vsynco polarity detect edge detect vpol one shot vedge internal bus clock overflow detect vof lvsie to interrupt logic 13-bit counter one shot overflow detect clk32/32.768 a 1 b s hsync sog sogsel a 1 b s polarity detect hpol comp vsync extractor extracted vsync b a 1 s h/v sync 2 s pulse generator svf shf clamp pulse generator clamp hsynco vflr vfhr hflr hfhr bpor coinv sout hover vpol vsie vsif $c00 detect lvsif hinvo hvocr[2:0] vsync (125khz) (6mhz) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 214 sync processor motorola 16.5.1 polarity detection 16.5.1.1 hsync polarity detection the hsync polarity detection circuit measures the length of high and low period of the hsync input. if the length of high is longer than l and the length of low is shorter than s , the hpol bit will be "0", indicating a negative polarity hsync in put. if the length of low is longer than l and the length of high is shorter than s , the hpol bit will be "1", indicating a positive polarity hsync input. the table below shows three possible cases for hsync polarity detection ? the conditions are selected by the hps[1:0] bits in the sync proc essor control register 1 (spcr1). 16.5.1.2 vsync polarity detection the vsync polarity detection circuit per forms a similar function as for hsync. if the length of high is l onger than 4ms and the length of low is shorter than 2ms, the vpol bit will be "0", indicating a negative polarity vsync input. if the length of low is longer t han 4ms and t he length of high is shorter than 2ms, the vpol bi t will be "1", indi cating a positive polarity vsync input. 16.5.1.3 composite sync polarity detection when a composite sync signal is t he input (comp = 1 for composite sync processing), the hpol bit = vpol bit, and the pol arity is detected using the vsync polarity detection criteria described in section 16.5.1.2 . polarity detection pulse width spcr1 ($0046) long is greater than ( l ) short is less than ( s ) hps1 hps0 7 s6 s00 3.5 s3 s1x 14 s12 s01 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor functional blocks mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 215 16.5.2 sync signal counters there are two counters: a 13-bit horiz ontal frequency counter to count the number of horizontal sync pulses within a 32ms or 8ms period; and a 13-bit vertical frequency counter to count the number of system clock cycles between two vertical sync pulse s. these two dat a can be read by the cpu to che ck the signal frequencies and to determine the video mode. the 13-bit vertical frequency register encompasses vertical frequency range from approximately 15hz to 128khz. due to the asynchronous timing between the incomi ng vsync signal and intern al system clock, there will be 1 count error on reading the vertical frequency registers (vfrs) for the same vertical frequency. the horizontal counter counts the pul ses on hsync pin input, and is uploaded to the hsync frequency registers (hfrs) every 32.768ms or 8.192ms. 16.5.3 polarity controlled hsynco and vsynco outputs the processed sync signals are out put on hsynco and vsynco when the corresponding bits in configurat ion register 0 ($001d) are set. the signal to these output pins depe nd on sout and comp bits (see table 16-3 ), with polarity contro lled by atpol, hinvo , and vinvo bits as shown in table 16-4 . table 16-3. sync output control sout comp sync outputs: vsynco and hsynco 1 x free-running pulse with negative polarity 00 sync outputs follow sync inputs vsync and hsync respectively, with polarity correction shown in table 16-4 . 01 hsynco follows the composite sync input and vsynco is the extracted vsync (3 to 14 s delay to composite input), with polarity correction shown in table 16-4 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 216 sync processor motorola when the sout bit is se t, the hsynco output is a free-running pulse with 2 s width. both hs ynco and vsynco outpu ts are negative polarity, with frequencies selected by the h & v sync output control register (hvocr). 16.5.4 clamp pulse output when the clampoe bit in sp iocr is set to "1", a clamp signal is output on the clamp pin. this clamp pulse is trigger ed either on the leading edge or the trailing edge of hsync, controlled by bpor bit, with the polarity controlled by the coinv bit. see figure 16-2 . clamp pulse output timing . figure 16-2. clamp pulse output timing table 16-4. sync output polarity atpol sout vinvo or hinvo sync outputs: vsynco/hsynco x 1 x free-running pulse with negative polarity 0 0 0 same polarity as sync input 0 0 1 inverted polarity of sync input 1 0 0 negative polarity sync output 1 0 1 positive polarity sync output pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s hsync (hpol = 1) clamp (bpor = 0) clamp (bpor = 1) hsync (hpol = 0) clamp (bpor = 0) clamp (bpor = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor registers mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 217 16.5.5 low vertical frequency detect logic monitors the value of the vsync frequency register (vfr), and sets the low vertical frequency flag (l vsif) when the value of vfr is higher than $c00 (frequency below 40.7hz). lvsif bit can generate an interrupt request to t he cpu when the lvsie bit is set and i-bit in the condition code re gister is "0". the lvsif bit can help the system to detect video off mode fast. 16.6 registers eight registers are associ ated with the sync proce ssor, they outlined in the following sections. 16.6.1 sync processor control & status register (spcsr) vsie ? vsync interrupt enable when this bit is set, the vsif flag is enabled to generate an interrupt request to the cpu. when vsie is cleared, the vsif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = vsif bit set will generat e interrupt request to cpu 0 = vsif bit set does not generate interr upt request to cpu address: $0040 bit 7654321bit 0 read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 = unimplemented figure 16-3. sync processor cont rol & status register (spcsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 218 sync processor motorola vedge ? vsync interrupt edge select this bit specifies the triggering edge of vsync interrupt. when it is "0", the rising edge of internal vsync signal which is either from the vsync pin or extracted from the composite input signal will set vsif flag. when it is "1", t he falling edge of internal vsync signal will set vsif flag. reset clears this bit. 1 = vsif bit will be set by rising edge of vsync 0 = vsif bit will be set by falling edge of vsync vsif ? vsync interrupt flag this flag is only set by the specified edge of the internal vsync signal, which is either from the vsync input pin or extracted from the composite sync input si gnal. the triggering edge is specified by the vedge bit. vsif generat es an interrupt reques t to the cpu if the vsie bit is also set. this bit is cleared by writing a "0" to it or by a reset. 1 = a valid edge is detected on the vsync 0 = no valid vsync is detected comp ? composite sync input enable this bit is set to enable the separato r circuit which extracts the vsync pulse from the composite sync input on hsync or sog pin (select by sogsel bit). the extracted vsync signa l is used as it were from the vsync input. reset clears this bit. 1 = composite sync input enabled 0 = composite sync input disabled vinvo ?tvsynco signal polarity this bit, toget her with the atpol bit in spcr1 controls the output polarity of the v synco signal (see table 16-5 ). hinvo ? hsynco signal polarity this bit, toget her with the atpol bit in spcr1 controls the output polarity of the h synco signal (see table 16-5 ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor registers mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 219 vpol ? vsync input polarity this bit indicates the polarity of the vsync input, or t he extracted vsync from a composite sync input (comp=1). reset clears this bit. 1 = vsync is positive polarity 0 = vsync is negative polarity hpol ?thsync input polarity this bit indicates the polarity of the hsync input. thi s bit equals the vpol bit when the co mp bit is set. re set clears this bit. 1 = hsync is positive polarity 0 = hsync is negative polarity 16.6.2 sync processor input/output control register (spiocr) vsyncs ? vsync input state this read-only bit reflects the l ogical state of the vsync input. hsyncs ? hsync input state this read-only bit reflects the l ogical state of the hsync input. table 16-5. atpol, vinvo, and hinvo setting atpol vinvo / hinvo sync outputs: vsynco/hsynco 0 0 same polarity as sync input 0 1 inverted polarity of sync input 1 0 negative polarity sync output 1 1 positive polarity sync output address: $0045 bit 7654321bit 0 read: vsyncs hsyncs coinv r sogsel clampoe bpor sout write: reset:00000000 = unimplemented r = reserved figure 16-4. sync processor input/output contro l register (spiocr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 220 sync processor motorola coinv ? clamp output invert this bit is set to inve rt the clamp pulse out put to negative. reset clears this bit. 1 = clamp output is set for negative pulses 0 = clamp output is set for positive pulses sogsel ?t sog select this bit selects either the hsync pin or sog pin as the composite sync signal input pin. reset clears this bit. 1 = sog pin is used as the composite sync input 0 = hsync pin is used as the composite sync input clampoe ?tclamp output enable this bit is set to enable the clamp pu lse output circuitry. reset clears this bit. 1 = clamp pulse circuit enabled 0 = clamp pulse circuit disabled bpor ? back porch this bit defines the tri ggering edge of the clamp pu lse output relative to the hsync input. reset clears this bit. 1 = clamp pulse is generated on the trailing edge of hsync 0 = clamp pulse is generated on the leading edge of hsync sout ? sync output enable this bit will select the output signals for the vsynco and hsynco pins. reset clears this bit. 1 = vsynco and hsynco outputs are internally generated free-running sync pul ses with frequencies determined by hvcor[2:0] bi ts in hvcor. 0 = vsynco and hsynco output s are processed vsync and hsync inputs respectively f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor registers mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 221 16.6.3 vertical frequency registers (vfrs) this register pair c ontains the 13-bit vertical frequency count value, an overflow bit, and the clamp pulse width selection bits. vf[12:0] ? vertical frame frequency this read-only 13-bit contains info rmation of the vertical frame frequency. an internal 13-bit counter counts the number of 8 s periods between two vsync pulses. the most significant 5 bits of the counted value is transferred to the hi gh byte register, and the least significant 8 bits is transferred to an interm ediate buffer. when the high byte register is read, the 8-bit counted val ue stored in the intermediate buffer will be uploaded to the lo w byte register. therefore, user program must read t he high byte register first, then low byte register in order to get the comple te counted value of one vertical frame. if the counter overfl ows, the overflow flag, vof, will be set, indicating the counter value st ored in the vfrs is meaningless. the data corresponds to th e period of one vertical frame. this register can be read to determine if t he frame frequency is valid, and to determine the video mode. address: $0041 bit 7654321bit 0 read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 figure 16-5. vertical frequency high register address: $0042 bit 7654321bit 0 read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 = unimplemented figure 16-6. vertical frequency low register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 222 sync processor motorola the frame frequency is calculated by: table 16-6 shows examples for the vert ical frequency regi ster, all vfr numbers are in hexadecimal. vof ? vertical frequen cy counter overflow this read-only bit is set when an over flow has occurred on the 13-bit vertical frequency counter. reset clears this bit, and will be updated every vertical frame. an overflow occurs when the period of vsync frame exceeds 64.768ms (a vertical frame fr equency lower than 15.258hz). 1 = a vertical frequency count er overflow has occurred 0 = no vertical frequency counter overflow has occurred table 16-6. sample ve rtical frame frequencies vfr max freq. min freq. vfr max freq. min freq. $02a0 186.20 hz 185.70 hz $0780 65.10 hz 65.00 hz $03c0 130.34 hz 130.07 hz $0823 60.04 hz 59.98 hz $03c1 130.21 hz 129.94 hz $0824 60.01 hz 59.95 hz $03c2 130.07 hz 129.80 hz $0825 59.98 hz 59.92 hz $04e2 100.08 hz 99.92 hz $09c4 50.02 hz 49.98 hz $04e3 100.00 hz 99.84 hz $09c5 50.00 hz 49.96 hz $04e4 99.92 hz 99.76 hz $09c6 49.98 hz 49.94 hz $06f9 70.07 hz 69.99 hz $1ffd 15.266 hz 15.262 hz $06fa 70.03 hz 69.95 hz $1ffe 15.264 hz 15.260 hz $06fb 69.99 hz 69.91 hz $1fff 15.262 hz 15.258 hz vertical frame frequency 1 vfr 1 48 t cyc --------------- ------------------ ----------------- - = 1 vfr 1 8 s ------------------- ------------------ - = for internal bus clock of 6 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor registers mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 223 cpw[1:0] ? clamp pulse width the cpw1 and cpw0 bits are used to select the output clamp pulse width. reset clears these bits, se lecting a default clamp pulse width between 0.33 s and 0.375 s. these bits al ways read as zeros. 16.6.4 hsync frequency registers (hfrs) this register pair contains the 13-bit hsyn c frequency count value and an overflow bit. table 16-7. clamp pulse width cpw1 cpw0 clamp pulse width 0 0 0.33 s to 0.375 s 010.5 s to 0.542 s 1 0 0.75 s to 0.792 s 112 s to 2.042 s address: $0043 bit 7654321bit 0 read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 figure 16-7. hsync fr equency high register address: $0044 bit 7654321bit 0 read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 = unimplemented figure 16-8. hsync frequency low register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 224 sync processor motorola hfh[7:0], hfl[4:0] ? ho rizontal line frequency this read-only 13-bit cont ains the number of ho rizontal lines in a 32ms window. an internal 13-bit counter counts the hsync pulses within a 32ms window in every 32.7 68ms period. if the fshf bit in spcr1 is set, only the most 11-bi ts (hfh[7:0] & hfl[4:2]) will be updated by the counter. thus, providi ng a hsync pulse count in a 8ms window in every 8.192ms. the most significant 8 bits of counted value is tr ansferred to the high byte register, and the l east significant 5 bits is transferred to an intermediate buffer. when the high byte regist er is read, the 5-bit counted value stored in the interm ediate buffer will be uploaded to the low byte register. therefore, user the program must read the high byte register first then low byte regist er in order to get the complete counted value of hsync pulses. if t he counter overflows, the overflow flag, hover, will be set, indicating the num ber of hsync pulses in 32ms are more than 8191 (2 13 ?1), i.e. a hsync frequency greater than 256khz. for the 32ms window, the hfhr and hflr are such that the frequency step unit in the 5-bit of hflr is 0.03125khz, and the step unit in the 8-bit hfhr is 1khz. therefore, the hsync frequency can be easily calculated by: hover ? hsync frequen cy counter overflow this read-only bit is set when an over flow has occurred on the 13-bit hsync frequency counter. reset clear s this bit, and will be updated every count period. an overflow occurs when the num ber hsync pulses exceed 8191, a hsync frequency great er than 256khz. 1 = a hsync frequency counter overflow has occurred 0 = no hsync frequency coun ter overflow has occurred hsync frequency = [ hfh + ( hfl 0.03125)]khz where: hfh is the value of hfh[7:0] hfl is the value of hfl[4:0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor registers mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 225 16.6.5 sync processor control register 1 (spcr1) lvsie ? low vsync interrupt enable when this bit is set, the lvsif fl ag is enabled to generate an interrupt request to the cpu. w hen lvsie is cleared, the lvsif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = low vsync interrupt enabled 0 = low vsync interrupt disabled lvsif ? low vsync interrupt flag this read-only bit is set when the va lue of vfr is higher than $c00 (vertical frame frequency below 40.7hz). lvsif generates an interrupt request to the cpu if the lvsi e is also set. this bit is cleared by writing a "0" to it or reset. 1 = vertical frequency is below 40.7hz 0 = vertical frequency is higher than 40.7hz hps[1:0] ? hsync input detecti on pulse width these two bits control the detecti on pulse width of hsync input. reset clears these two bits, sett ing a default middle frequency of hsync input. address: $0046 bit 7654321bit 0 read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:00000000 = unimplemented r = reserved figure 16-9. sync processor co ntrol register 1 (spcr1) table 16-8. hsync polarity detection pulse width hps1 hps0 polarity detection pulse width 0 0 long > 7 s and short < 6 s 1 x long > 3.5 s and short < 3 s 0 1 long > 14 s and short < 12 s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 226 sync processor motorola atpol ? auto polarity this bit, toget her with the vinvo or hinvo bits in spcsr controls the output polarity of the vsynco or hsynco signals respectively. reset clears this bit (see table 16-9 ). fshf ? fast horizontal frequency count this bit is set to s horten the measurement cycle of the horizontal frequency. if it is set, only hfh[7:0] and hfl[4:2] will be updated by the hsync counter, pr oviding a count in a 8ms window in every 8.192ms, with hfl[1:0] reading as zeros. therefore, user can determine the horizontal frequency c hange within 8.192ms to protect critical circuitry. re set clears this bit. 1 = number of hsync pulse s is counted in an 8ms window 0 = number of hsync pulses is counted in a 32ms window 16.6.6 h&v sync output control register (hvocr) table 16-9. atpol, vinvo, and hinvo setting atpol vinvo / hinvo sync outputs: vsynco/hsynco 0 0 same polarity as sync input 0 1 inverted polarity of sync input 1 0 negative polarity sync output 1 1 positive polarity sync output address: $0047 bit 7654321bit 0 read: r 0000 hvocr2 hvocr1 hvocr0 write: reset:00000000 = unimplemented r = reserved figure 16-10. h&v sy nc output control register (hvocr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor system operation mc68HC908BD48 ? rev. 2.0 data sheet motorola sync processor 227 hvocr[2:0] ? h&v ou tput select bits these three bits select the frequencies of t he internal generated free-running sync pulse s for output to hsyn co and vsynco pins, when the sout bit is set in the spiocr. reset clears these bits, setting a default horizont al frequency of 31.2 5khz and a vertical frequency of 60hz, a video mode of 640 480. 16.7 system operation this sync processor is designed to a ssist in determining the video mode of incoming hsync and vsy nc of various frequenc ies and polarities, and dpms modes. in the dpms standard, a no sync pulses definition can be detected when the value of the hsync frequency register (the number of hsync pulses) is less than one or when the vof bit is set. since the hsync frequency register is updated repeatedly in every 32.768ms, and a valid vsync must have a frequen cy greater than 40.7hz, a valid vsync pul se will arrive withi n the 32.768ms window. therefore, the user should read t he hsync frequency register every 32.768ms to determine the presence of hsync and/or vsync pulses. table 16-10. free-r unning hsync and vsync options hvocr hsynco vsynco video mode pulse width frequency pulse width frequency 000 negative 2 s 31.25khz negative 192 s 59.98 hz 640 480 001 negative 2 s 43.48khz negative 138 s 84.92 hz 640 480 010 negative 2 s 48.78khz negative 123 s 60.00 hz 1024 768 011 negative 2 s 54.05khz negative 111 s 84.98 hz 800 600 100 negative 2 s 60.61khz negative 99 s 75.01 hz 1024 768 101 negative 2 s 80.00khz negative 75 s 74.98 hz 1280 1024 110 negative 2 s 90.91khz negative 66 s 84.96 hz 1280 1024 111 negative 2 s 105.26khz negative 57 s 85.02 hz 1600 1200 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sync processor data sheet mc68HC908BD48 ? rev. 2.0 228 sync processor motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 229 data sheet ? mc68HC908BD48 section 17. input/output (i/o) ports 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 17.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 234 17.3.3 port a options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 237 17.4.3 port b options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.5.3 port c options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.6.3 port d options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.7.3 port e options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.2 introduction thirty-two (32) bidi rectional input-output (i/o) pins form four parallel ports. all i/o pins are progr ammable as inputs or outputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 230 input/output (i/o) ports motorola note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o ports do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. table 17-1. i/o port register summary addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: 0 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports introduction mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 231 $0007 data direction register d (ddrd) read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 00000 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: 00000 ddre2 ddre1 ddre0 write: reset:00000000 $001d configuration register 0 (config0) read: hsyncoe vsyncoe soge 00000 write: reset:00000000 $0028 pwm control register 1 (pwmcr1) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 $0049 port d configuration register (pdcr) read: 0 iicdate iicscle clampe ddcscle ddcdate usbd?e usbd+e write: reset:00000000 $0059 pwm control register 2 (pwmcr2) read: pwm15e pwm14e pwm13e pwm12e pwm11e pwm10e pwm9e pwm8e write: reset:00000000 table 17-1. i/o port register summary (continued) addr.register name bit 7654321bit 0 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 232 input/output (i/o) ports motorola table 17-2. port contro l register bits summary port bit ddr module control pin module register control bit a 0 ddra0 pwm pwmcr2 $0059 pwm8e pta0/pwm8 1 ddra1 pwm9e pta1/pwm9 2 ddra2 pwm10e pta2/pwm10 3 ddra3 pwm11e pta3/pwm11 4 ddra4 pwm12e pta4/pwm12 5 ddra5 pwm13e pta5/pwm13 6 ddra6 pwm14e pta6/pwm14 7 ddra7 pwm15e pta7/pwm15 b 0 ddrb0 pwm pwmcr1 $0028 pwm0e ptb0/pwm0 1 ddrb1 pwm1e ptb1/pwm1 2 ddrb2 pwm2e ptb2/pwm2 3 ddrb3 pwm3e ptb3/pwm3 4 ddrb4 pwm4e ptb4/pwm4 5 ddrb5 pwm5e ptb5/pwm5 6 ddrb6 pwm6e ptb6/pwm6 7 ddrb7 pwm7e ptb7/pwm7 c 0 ddrc0 adc adscr $005d adch[4:0] ptc0/adc0 1 ddrc1 ptc1/adc1 2 ddrc2 ptc2/adc2 3 ddrc3 ptc3/adc3/ 4 ddrc4 ptc4/adc4 5 ddrc5 ptc5/adc5 d 0 ddrd0 usb pdcr $0049 d+e ptd0/d+ 1 ddrd1 d?e ptd1/d? 2 ddrd2 ddc12ab ddcdate ptd2/ddcsda 3 ddrd3 ddcscle ptd3/ddcscl 4 ddrd4 sync clampe ptd4/clamp 5 ddrd5 mmiic iicscle ptd5/iicscl 6 ddrd6 iicdate ptd6/iicsda e 0 ddre0 sync/tim config0 $001d soge pte0/sog/tch0 1 ddre1 sync hsyncoe pte1/hsynco 2 ddre2 vsyncoe pte2/vsynco f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 233 17.3 port a port a is an 8-bit special- function port that shares all eight of its pins with the pulse width modulator (pwm). 17.3.1 port a data register the port a data register (p ta) contains a data latch for each of the eight port a pins. pta7?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. pwm15?pwm8 ? pw m outputs 15?8 the pwm output enable bits pwm 15e?pwm8e, in pwm control register 2 (pwmcr2) enabl e port a pins as pwm output pins. (see 17.3.3 port a options .) address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternate function: pwm15 pwm14 pwm13 pwm12 pwm11 pwm10 pwm9 pwm8 figure 17-1. port a data register (pta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 234 input/output (i/o) ports motorola 17.3.2 data direction register a data direction register a (ddra) dete rmines whether each port a pin is an input or an output. wr iting a logic 1 to a d dra bit enables the output buffer for the corresponding port a pi n; a logic 0 dis ables the output buffer. ddra7?ddra0 ? data direc tion register a bits these read/write bits control port a data direction. reset clears ddra7?ddra0, configuring al l port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 17-3 shows the port a i/o logic. figure 17-3. port a i/o circuit address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 17-2. data direct ion register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 235 when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-3 summarizes the operation of the port a pins. 17.3.3 port a options the pwm control register 2 (pwmcr2) selects the port a pins for pwm function or as standard i/o function. see 11.4.2 pwm control registers 1 and 2 (pwmcr1:pwmcr2) . pwm15e?pwm8e ? pw m output enable 15?8 setting a bit to "1" wi ll configure the corr esponding ptax/pwmx pin for pwm output func tion. reset clears these bits. 1 = ptax/pwmx pin confi gured as pwmx output pin 0 = ptax/pwmx pin confi gured as standard i/o pin table 17-3. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 00x (1) input, hi-z (2) ddra7?ddra0 pin pta7?pta0 (3) x 1 x output ddra7?ddra0 pta7?pta0 pta7?pta0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. address: $0059 bit 7654321bit 0 read: pwm15e pwm14e pwm13e pwm12e pwm11e pwm10e pwm9e pwm8e write: reset:00000000 figure 17-4. pwm contro l register 1 (pwmcr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 236 input/output (i/o) ports motorola 17.4 port b port b is an 8-bit special- function port that shares all eight of its pins with the pulse width modulator (pwm). 17.4.1 port b data register the port b data register (p tb) contains a data latch for each of the eight port pins. ptb7?ptb0 ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. pwm7?pwm0 ? pwm outputs 7?0 the pwm output enable bits pwm7 e?pwm0e, in pwm control register 1 (pwmcr1) enabl e port b pins as pwm output pins. (see 17.4.3 port b options .) address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternate function: pwm7 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 figure 17-5. port b data register (ptb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 237 17.4.2 data direction register b data direction register b (ddrb) dete rmines whether each port b pin is an input or an output. wr iting a logic 1 to a d drb bit enables the output buffer for the corresponding port b pi n; a logic 0 dis ables the output buffer. ddrb7?ddrb0 ? data direc tion register b bits these read/write bits control port b data direction. reset clears ddrb7?ddrb0, configuring al l port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. figure 17-7 shows the port b i/o logic. figure 17-7. port b i/o circuit address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 17-6. data direct ion register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 238 input/output (i/o) ports motorola when bit ddrbx is a l ogic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-4 summarizes the operation of the port b pins. 17.4.3 port b options the pwm control register 1 (pwmcr1) selects the port b pins for pwm function or as standard i/o function. see 11.4.2 pwm control registers 1 and 2 (pwmcr1:pwmcr2) . pwm7e?pwm0e ? pwm output enable 7?0 setting a bit to "1" wi ll configure the corr esponding ptbx/pwmx pin for pwm output func tion. reset clears these bits. 1 = ptbx/pwmx pin confi gured as pwmx output pin 0 = ptbx/pwmx pin confi gured as standard i/o pin table 17-4. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) input, hi-z (2) ddrb7?ddrb0 pin ptb7?ptb0 (3) 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. address: $0028 bit 7654321bit 0 read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 figure 17-8. pwm contro l register 1 (pwmcr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 239 17.5 port c port c is an 6-bit special-function port that shares all six of its pins with the analog-to-digital converter (a dc) module. 17.5.1 port c data register the port c data register (ptc) contains a data latch for each of the seven port c pins. ptc5?ptc0 ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. adc5?adc0 ? analog-t o-digital input bits adc5?adc0 are pins used for t he input channels to the analog-to- digital converter module. the channel select bits in the adc status and control register define which port c pi n will be used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. address: $0002 bit 7654321bit 0 read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternate function: adc5 adc4 adc3 adc2 adc1 adc0 = unimplemented figure 17-9. port c data register (ptc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 240 input/output (i/o) ports motorola note: care must be taken w hen reading port c while applying analog voltages to adc5?adc0 pins . if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptcx/adcx pin, while ptc is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. 17.5.2 data direction register c data direction register c (ddrc) determines whet her each port c pin is an input or an output. writ ing a logic 1 to a dd rc bit enables the output buffer for the corresponding port c pi n; a logic 0 dis ables the output buffer. ddrc5?ddrc0 ? data direc tion register c bits these read/write bits control port c data direction. reset clears ddrc5?ddrc0, configuring al l port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 17-11 shows the port c i/o logic. address: $0006 bit 7654321bit 0 read: 0 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 17-10. data direct ion register c (ddrc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 241 figure 17-11. port c i/o circuit when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-5 summarizes the operation of the port c pins. 17.5.3 port c options the adch4?adch0 bi ts in the adc status and control register (adscr) defines which ptcx/adcx pin is used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. see 12.8.1 adc status and control register . read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus table 17-5. port c pin functions ptcpue bit ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 0 x input, hi-z (2) ddrc5?ddrc0 pin ptc5?ptc0 (3) x 1 x output ddrc5?ddrc0 ptc5?ptc0 ptc5?ptc0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 242 input/output (i/o) ports motorola 17.6 port d port d is an 7-bit special-function port t hat shares two of its pins with the multi-master iic (mmiic) module, one of its pins with the sync processor, two of its pins with the ddc12ab module, and tw o of its pins with the usb module. note: ptd1?ptd0 are 3.3v pins. 17.6.1 port d data register the port d data register (ptd) contains a data latch for each of the eight port d pins. ptd6?ptd0 ? port d data bits these read/write bits are software-p rogrammable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. iicsda, iicscl ? multi-mast er iic data and clock pins the ptd6/iicsda and ptd5/iicscl pi ns are multi-master iic data and clock pins. when the iicdate and iicscle bits in the port d configuration regist er (pdcr) is clear, the ptd6/iicsda and ptd5/iicscl pins are availabl e for general-pur pose i/o. see 17.6.3 port d options . address: $0003 bit 7654321bit 0 read: 0 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternate function: iicsda iicscl clamp ddcscl ddcsda d? d+ = unimplemented figure 17-12. port d da ta register (ptd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 243 clamp ? sync processor clamp pulse output pin the ptd4/clamp pin is the sync pr ocessor clamp pulse output pin. when the clampe bit in the port d configuration regi ster (pdcr) is clear, the ptd4/clamp pin is avail able for general-pur pose i/o. see 17.6.3 port d options . ddcscl, ddcsda ? ddc12ab data and clock pins the ptd3/ddcscl and ptd2/ddcsda pins are ddc12ab clock and data pins respectively. when the ddcscle and ddcdate bits in the port d configuration r egister (pdcr) is clear, the ptd3/ddcscl and ptd2/ddcsda pins are available for general- purpose i/o. see 17.6.3 port d options . d?, d+ ? usb i/o pins the ptd1/d? and ptd0/d+ pins ar e the usb port pins. when the usbd?e and usbd+e bits in the port d configuration register (pdcr) is clear, the ptd1/d? and ptd0/d+ pins are avail able for general- purpose i/o. see 17.6.3 port d options . 17.6.2 data direction register d data direction register d (ddrd) determines whet her each port d pin is an input or an output. writ ing a logic 1 to a dd rd bit enables the output buffer for the corresponding port d pi n; a logic 0 dis ables the output buffer. ddrd6?ddrd0 ? data direc tion register d bits these read/write bits control port d data direction. reset clears ddrd6?ddrd0, configuring al l port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input address: $0007 bit 7654321bit 0 read: 0 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 17-13. data direct ion register d (ddrd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 244 input/output (i/o) ports motorola note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction regist er d bits fr om 0 to 1. figure 17-14 shows the port d i/o logic. figure 17-14. port d i/o circuit when bit ddrdx is a l ogic 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operation of t he port d pins. read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus table 17-6. port d pin functions ptdpue bit ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 0 x input, hi-z (2) ddrd6?ddrd0 pin ptd6?ptd0 (3) x 1 x output ddrd6?ddrd0 ptd6?ptd0 ptd6?ptd0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 245 17.6.3 port d options the port d configuration register (p dcr) selects the port d pins for module function or as standard i/o function. iicdate ? mmiic data pin enable this bit is set to conf igure the ptd6/iicsda pi n for iicsda function. reset clears this bit. 1 = ptd6/iicsda pin conf igured as iicsda pin 0 = ptd6/iicsda pin conf igured as standard i/o pin iicscle ? mmiic clock pin enable this bit is set to conf igure the ptd5/iicscl pi n for iicscl function. reset clears this bit. 1 = ptd5/iicscl pin conf igured as iicscl pin 0 = ptd5/iicscl pin conf igured as standard i/o pin clamp ? clamp pin enable this bit is set to conf igure the ptd4/clamp pin for sync processor clamp pulse output. reset clears this bit. 1 = ptd4/clamp pin configured as clamp pin 0 = ptd4/clamp pin confi gured as standard i/o pin ddcscle ? ddc clock pin enable this bit is set to c onfigure the ptd3/ddc scl pin for ddcscl function. reset clears this bit. 1 = ptd3/ddcscl pin configured as ddcscl pin 0 = ptd3/ddcscl pin confi gured as standard i/o port address: $0049 bit 7654321bit 0 read: 0 iicdate iicscle clampe ddcscle ddcdate usbd?e usbd+e write: reset:00000000 = unimplemented figure 17-15. port d confi guration register (pdcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 246 input/output (i/o) ports motorola ddcdate ? ddc data pin enable this bit is set to configure the ptd2/ ddcsda pin for ddcsda function. reset clears this bit. 1 = ptd2/ddcsda pin conf igured as ddcsda pin 0 = ptd2/ddcsda pin configur ed as standard i/o port usbd?e ? usb d? pin enable this bit is set to conf igure the ptd1/d? pin fo r d? function. reset clears this bit. 1 = ptd1/d? pin conf igured as d? pin 0 = ptd1/d? pin confi gured as standard i/o port usbd+e ? usb d+ pin enable this bit is set to conf igure the ptd0/d+ pin fo r d+ function. reset clears this bit. 1 = ptd0/d+ pin conf igured as d+ pin 0 = ptd0/d+ pin configur ed as standard i/o port f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 247 17.7 port e port e is a 3-bit special-f unction port that shares all of its pins with the sync processor. 17.7.1 port e data register the port e data register contains a data latch for each of the t hree port e pins. pte2?pte0 ? port e data bits pte2?pte0 are read/write, softwa re programmable bits. data direction of each port e pin is und er the control of the corresponding bit in data direction register e. vsynco ? vsync output the pte2/vsynco pin is the vsync output from the sync processor. when the vsyncoe is clear, the pt e2/vsynco pin is available for general-purpose i/o. see 17.7.3 port e options . hsync ? hsync output the pte1/hsynco pin is the hsync output from the sync processor. when the hsyncoe is clear, the pt e1/hsynco pin is available for general-purpose i/o. see 17.7.3 port e options . address: $0008 bit 7654321bit 0 read: 00000 pte2 pte1 pte0 write: reset: unaffected by reset alternate function: vsynco hsynco sog or tch0 = unimplemented figure 17-16. port e da ta register (pte) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 248 input/output (i/o) ports motorola sog/tch0 ? sog out put or tch0 input the pte0/sog/tch0 pin is the sog input for the sync processor or the input capture of th e tim channel 0. see 17.7.3 port e options . 17.7.2 data direction register e data direction register e (ddre) dete rmines whether each port e pin is an input or an output. wr iting a logic 1 to a d dre bit enables the output buffer for the corresponding port e pi n; a logic 0 dis ables the output buffer. ddre2?ddre0 ? data direc tion register e bits these read/write bits control port e data direction. reset clears ddre2?ddre0, configuring al l port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. figure 17-18 shows the port e i/o logic. address: $000c bit 7654321bit 0 read: 00000 ddre2 ddre1 ddre0 write: reset:00000000 = unimplemented figure 17-17. data direct ion register e (ddre) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e mc68HC908BD48 ? rev. 2.0 data sheet motorola input/output (i/o) ports 249 figure 17-18. port e i/o circuit when bit ddrex is a l ogic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-7 summarizes the operation of the port e pins. read ddre ($0009) write ddre ($0009) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus table 17-7. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) input, hi-z (2) ddre2?ddre0 pin pte2?pte0 (3) 1 x output ddre2?ddre0] pte2?pte0 pte2?pte0 notes: 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register , but does not affect input. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC908BD48 ? rev. 2.0 250 input/output (i/o) ports motorola 17.7.3 port e options the configuration register 0 (conf ig0) selects the port e pins for module function or as standard i/o function. hsyncoe ? vsynco enable this bit is set to configure the pte1/hsynco pin for hsynco output function. reset clears this bit. 1 = pte1/hsynco pin configured as hsynco pin 0 = pte1/hsynco pi n configured as standard i/o pin vsyncoe ? vsynco enable this bit is set to configure the pte2/vsynco pin fo r vsynco output function. reset clears this bit. 1 = pte2/vsynco pin configured as vsynco pin 0 = pte2/vsynco pi n configured as standard i/o pin soge ? sog enable this bit is set to conf igure the pte0/sog/tch 0 pin for sog output function. reset clears this bit. 1 = pte0/sog/tch0 pin configured as sog pin 0 = pte0/sog/tch0 pin configured as standard i/o or tch0 pin. tch0 function is configured by els0b and els0a bits in tsc0 (bits 3 and 2 in $0010). address: $001d bit 7654321bit 0 read: hsyncoe vsyncoe soge 00000 write: reset:00000000 = unimplemented figure 17-19. configuratio n register 0 (config0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola external interrupt (irq) 251 data sheet ? mc68HC908BD48 section 18. external interrupt (irq) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 18.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 255 18.7 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 255 18.2 introduction the irq (external interrupt) module pr ovides a maskable interrupt input. 18.3 features features of the irq module include: a dedicated external interrupt pin (irq ) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup resistor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68HC908BD48 ? rev. 2.0 252 external interrupt (irq) motorola 18.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 18-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears t he latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate ackn owledge bit in the in terrupt status and control register (intscr). writing a logic 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falli ng-edge or falling-edge and low-level- triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, softwa re clear, or reset occurs. when an interrupt pin is both falli ng-edge and low-level-triggered, the interrupt remains set until both of the following occur: vector fetch or software clear return of the interr upt pin to logic 1 the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear the la tch and the mode control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bit in the intscr mask a ll external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola external interrupt (irq) 253 note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external interrupt requests. figure 18-1. irq module block diagram irq ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device table 18-1. irq i/o register summary addr.register name bit 7654321bit 0 $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68HC908BD48 ? rev. 2.0 254 external interrupt (irq) motorola 18.5 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falling- edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the interrupt stat us and control register (intscr). the ack bit is useful in appl ications that poll the irq pin and require software to clear the irq la tch. writing to the ack bit prior to leaving an interrupt service r outine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit another interrupt request. if the irq mask bit, imask, is clear, t he cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software cl ear and the return of the irq pin to logic 1 may occur in any order. the inte rrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby cl earing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. use the bih or bil in struction to read the logic level on the irq pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq module during break interrupts mc68HC908BD48 ? rev. 2.0 data sheet motorola external interrupt (irq) 255 note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. 18.6 irq module during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latc h during the break state. see section 20. break module (brk) . to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect cpu interrupt fl ags during the break stat e, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), writing to the ack bit in the irq status and control regi ster during the br eak state has no effect on the ir q interrupt flags. 18.7 irq status and control register the irq status and control register (intscr) controls and monitors operation of the irq module. the intscr: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering se nsitivity of the irq interrupt pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68HC908BD48 ? rev. 2.0 256 external interrupt (irq) motorola irqf ? irq flag bit this read-only status bi t is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/lev el select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on fa lling edges and low levels 0 = irq interrupt requests on falling edges only address: $001e bit 7654321bit 0 read: irqf 0 imask mode write: ack reset:00000000 = unimplemented figure 18-2. irq status and control register (intscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola computer operating properly (cop) 257 data sheet ? mc68HC908BD48 section 19. computer operating properly (cop) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 19.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 19.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 19.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 19.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 19.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 260 19.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 19.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 19.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 19.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 19.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 262 19.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68HC908BD48 ? rev. 2.0 258 computer operating properly (cop) motorola 19.3 functional description figure 19-1 shows the structure of the cop module. figure 19-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 oscxclk cycles, depending on the state of the co p rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 oscxclk cycle overflow option, a 24 mhz crystal gives a co p timeout period of 10.922ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by cleari ng the cop count er and stages 12 through 5 of the prescaler. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. copctl write oscxclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear cop module copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config1) cop rate sel (coprs from config1) clear stages 5?12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) i/o signals mc68HC908BD48 ? rev. 2.0 data sheet motorola computer operating properly (cop) 259 a cop reset pulls the rst pin low for 32 oscxcl k cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq1 is held at v tst . during the br eak state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 19.4 i/o signals the following paragraphs descri be the signals shown in figure 19-1 . 19.4.1 oscxclk oscxclk is the crystal oscillator output signal . oscxclk frequency is equal to the crystal frequency. 19.4.2 stop instruction the stop instruction cl ears the cop prescaler. 19.4.3 copctl write writing any value to the cop control register (copctl) (see 19.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the prescaler. reading the cop cont rol register retu rns the low byte of the reset vector. 19.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 oscxclk cycles after power-up. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68HC908BD48 ? rev. 2.0 260 computer operating properly (cop) motorola 19.4.5 internal reset an internal reset clears the co p prescaler and the cop counter. 19.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 19.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration register 1 (see figure 19-2 ). 19.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the configurati on register 1(see figure 19-2 ). coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop timeout period = 2 13 ? 2 4 oscxclk cycles 0 = cop timeout period = 2 18 ? 2 4 oscxclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: 0 0 0 0 ssrec coprs stop copd write: reset:00000000 = unimplemented figure 19-2. configurati on register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register mc68HC908BD48 ? rev. 2.0 data sheet motorola computer operating properly (cop) 261 19.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 19.6 interrupts the cop does not generate cpu interrupt requests. 19.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is enter ed by having blank rese t vectors and not having v tst on the irq pin, the cop is automatic ally disabled until a por occurs. 19.8 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 19-3. cop cont rol register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68HC908BD48 ? rev. 2.0 262 computer operating properly (cop) motorola 19.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 19.8.2 stop mode stop mode turns off the oscxclk input to the cop and clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. to prevent inadvertently turning off t he cop with a stop instruction, a configuration option is av ailable that disables the stop instruction. when the stop bit in the config uration register has the stop instruction is disabled, execution of a stop in struction results in an illegal opcode reset. 19.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola break module (brk) 263 data sheet ? mc68HC908BD48 section 20. break module (brk) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 20.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 20.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 266 20.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .266 20.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 266 20.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 266 20.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 20.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 20.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 20.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 267 20.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 270 20.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) data sheet mc68HC908BD48 ? rev. 2.0 264 break module (brk) motorola 20.3 features features of the br eak module include: accessible input/output (i/o) regi sters during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 20.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal to the cpu. the cpu then loads the instruct ion register with a software interrupt instruction (swi) afte r completion of the current cpu instruction. the progr am counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 20-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) functional description mc68HC908BD48 ? rev. 2.0 data sheet motorola break module (brk) 265 figure 20-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break table 20-1. break modul e i/o register summary addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset:00000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) data sheet mc68HC908BD48 ? rev. 2.0 266 break module (brk) motorola 20.4.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bi ts during the break state. 20.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 20.4.3 tim during break interrupts a break interrupt stops the timer counters. 20.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 20.5 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 20.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see section 7. system in tegration module (sim) ). clear the sbsw bit by writi ng logic 0 to it. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers mc68HC908BD48 ? rev. 2.0 data sheet motorola break module (brk) 267 20.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 20.6 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) sim break status register (sbsr) sim break flag control register (sbfcr) 20.6.1 break status and control register the break status and control register (brkscr) contai ns break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 20-2. break status an d control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) data sheet mc68HC908BD48 ? rev. 2.0 268 break module (brk) motorola brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) br eak address match 0 = (when read) no break address match 20.6.2 break address registers the break address register s (brkh and brkl) contai n the high and low bytes of the desired brea kpoint address. reset clears the break address registers. 20.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode a fter exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 20-3. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 20-4. break addr ess register low (brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers mc68HC908BD48 ? rev. 2.0 data sheet motorola break module (brk) 269 sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset:00000000 note: writing a logic 0 clears sbsw. r= reserved figure 20-5. sim break stat us register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) data sheet mc68HC908BD48 ? rev. 2.0 270 break module (brk) motorola 20.6.4 sim break flag control register the sim break flag control register (s bfcr) contains a bit that enables software to clear status bits wh ile the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 20-6. sim break flag c ontrol register (sbfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola electrical specifications 271 data sheet ? mc68HC908BD48 section 21. electrical specifications 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 21.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 272 21.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 273 21.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 21.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 274 21.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.9 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 21.10 usb dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . 277 21.11 usb low speed source electrical characterist ics. . . . . . . . . 278 21.12 timer interface module characteristics . . . . . . . . . . . . . . . . . 278 21.13 ddc12ab/mmiic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 21.13.1 ddc12ab/mmiic interface input signal timing . . . . . . . . 279 21.13.2 ddc12ab/mmiic interface output signal timing . . . . . . . 279 21.14 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 21.15 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 21.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC908BD48 ? rev. 2.0 272 electrical specifications motorola 21.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 21.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd .) characteristic symbol value unit supply voltage v dd ?0.3 to +5.5 v input voltage v in v ss ?0.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma note: 1. voltages referenced to v ss . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications functional operating range mc68HC908BD48 ? rev. 2.0 data sheet motorola electrical specifications 273 21.4 functional operating range 21.5 thermal characteristics characteristic symbol value unit operating temperature range t a 0 to 85 c operating voltage range v dd 4.5 to 5.5 v characteristic symbol value unit thermal resistance qfp (44 pins) sdip (42 pins) ja 95 60 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) k p d (t a + 273 c ) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c notes: 1. power dissipation is a function of temperature. 2. k is a constant unique to the de vice. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC908BD48 ? rev. 2.0 274 electrical specifications motorola 21.6 dc electrical characteristics characteristic symbol min typ (2) max unit output high voltage (i load = ?2.0ma) all ports (except ptd0 and ptd1) v oh v dd ? 0.8 ??v output low voltage (i load = 1.6ma) all ports (except ptd0 and ptd1) v ol ??0.4v input high voltage all ports (except ptd0 and ptd1), irq , rst osc1, ptd0, ptd1 vsync, hsync v ih 0.7 v dd 0.7 v reg 2.0 ? ? ? v dd v reg v dd v v input low voltage all ports (except ptd0 and ptd1), irq , rst osc1, ptd0, ptd1 vsync, hsync v il v ss v ss v ss ? ? ? 0.2 v dd 0.2 v reg 0.8 v v v dd supply current run, usb active run, usb suspended (3) wait (4) stop (5) 0 c to 85 c i dd ? ? ? ? 10 8 4 2 15 12 8 5 ma ma ma ma i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) v por 0?100mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 2.5 9 v pull-up resistor rst , irq r pu 20 45 65 k ? low-voltage inhibit, trip falling voltage v tripf 3.4 3.6 3.8 v low-voltage inhibit, trip rising voltage v tripr 3.6 3.8 4.0 v low-voltage inhibit reset/recover hysteresis v hys ?200?mv notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average meas urements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 15 pf on osc2. all ports configured as i nputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external sq uare wave clock source (f oscxclk = 24mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 15pf on osc2; usb in suspend mode, 15 k ? 5% termination resistors on d+ and d? pins; all ports config- ured as inputs; osc2 capacit ance linearly affects wait i dd . 5. stop i dd measured with usb in suspend mode, osc1 grounded, 1.5 k ? 1% pull-up resistor on d+ pin and 15 k ? 1% pull-down resistors on d+ and d? pins, no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low exte rnally until minimum v dd is reached. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications control timing mc68HC908BD48 ? rev. 2.0 data sheet motorola electrical specifications 275 21.7 control timing 21.8 oscillator characteristics characteristic symbol min max unit internal operating frequency (2) f op ?6mhz rst input pulse width low (3) t irl 50 ? ns notes: 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. some modules may require a minimum frequency greater th an dc for proper operation; see appropriate table for this information. 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. characteristic symbol min typ max unit crystal frequency (1) f oscxclk ? 24 ? mhz external clock reference frequency (1), (2) f oscxclk dc ? 24 mhz crystal load capacitance (3) c l ?30 ? pf crystal fixed capacitance (3) c 1 ?15 ? pf crystal tuning capacitance (3) c 2 ?15 ? pf feedback bias resistor r b ?10 ? m ? series resistor (3), (4) r s ?? ? notes: 1. the sync processor module is designed to function at f oscxclk = 24mhz. the values given here are oscillator specifi- cations. 2. no more than 10% duty cycle deviation from 50% 3. quoted values are for reference only. actual values depend on application and crystal performance. please consult crystal vendor data sheet 4. not required for high frequency crystals f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC908BD48 ? rev. 2.0 276 electrical specifications motorola 21.9 adc characteristics characteristic (1) symbol min max unit comments supply voltage v ddad 4.5 (v dd min) 5.5 (v dd max) v input voltages v adin 0 v dd v resolution b ad 88bits absolute accuracy (v ss = 0 v, v dd = 5 v 10%) a ad ? 2 lsb includes quantization adc internal clock f adic 0.375 6 mhz t aic = 1/f adic , tested only at 1.5 mhz conversion range r ad v ss v dd v power-up time t adpu 16 t aic cycles conversion time t adc 12 13 t aic cycles sample time (2) t ads 4? t aic cycles zero input reading (3) z adi 00 02 hex full-scale reading (3) f adi fd ff hex input capacitance c adi ? 8 pf not tested input leakage (4) port c ?? 1 a notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current. 2 3 ------ 2 3 ------ f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications usb dc electrical characteristics mc68HC908BD48 ? rev. 2.0 data sheet motorola electrical specifications 277 figure 21-1. adc input vo ltage vs. step readings 21.10 usb dc electri cal characteristics characteristic symbol conditions min typ max unit hi-z state data line leakage i lo 0v electrical specifications ddc12ab/mmiic timing mc68HC908BD48 ? rev. 2.0 data sheet motorola electrical specifications 279 21.13 ddc12ab/mmiic timing 21.13.1 ddc12ab/mmiic interface input signal timing 21.13.2 ddc12ab/mmiic interface output signal timing characteristic symbol min max unit start condition hold time t hd.sta 2? t cyc clock low period t low 4? t cyc clock high period t high 4? t cyc data set-up time t su.dat 250 ? ns data hold time t hd.dat 0?ns start condition set-up time (for repeated start condition only) t su.sta 2? t cyc stop condition set-up time t su.sto 2? t cyc notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. characteristic symbol min max unit sda/scl rise time (2) t r ?1 s sda/scl fall time t f ? 300 ns data set-up time t su.dat t low ?ns data hold time t hd.dat 0?ns notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. with 200pf loading on the sda/scl pins. t hd.sta t low t high t su.dat t hd.dat t su.sto sda scl t su.sta f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC908BD48 ? rev. 2.0 280 electrical specifications motorola 21.14 sync pr ocessor timing characteristic symbol min max unit vsync input sync pulse t vi.sp 82048 s hsync input sync pulse t hi.sp 0.1 6 s vsync to vsynco delay (8pf loading) t vvd 30 40 s hsync to hsynco delay (8pf loading) t hhd 30 40 s notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications memory characteristics mc68HC908BD48 ? rev. 2.0 data sheet motorola electrical specifications 281 21.15 memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 2?v flash program bus clock frequency ? 1 ? mhz flash read bus clock frequency f read (1) 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8.4m hz flash page erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 2?ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 4?ms flash pgm/erase to hven set up time t nvs 5? s flash high-voltage hold time t nvh 5? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 10 ? s flash program time t prog 20 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1? s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 64) t hv max. ?4ms flash row erase endurance (6) 6. the minimum row endurance value specifies each ro w of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash row program endurance (7) 7. the minimum row endurance value specifies each ro w of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ?10?years notes: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC908BD48 ? rev. 2.0 282 electrical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola mechanical specifications 283 data sheet ? mc68HC908BD48 section 22. mechanical specifications 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22.4 42-pin shrink dual in -line package (sdip) . . . . . . . . . . . . . . 284 22.5 44-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 285 22.2 introduction this section gives t he dimensions for: 42-pin shrink dual in -line package (case #858) 44-pin plastic quad flat pack (case #824a) 22.3 42-pin shrink dual in-line package (sdip) figure 22-1. 42-pin sdip (case #858) ?a? 42 22 121 ?b? seating plane ?t? s a m 0.25 (0.010) t s b m 0.25 (0.010) t l h m j 42 pl d 42 pl f g n k c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010). dim min max min max millimeters inches a 1.435 1.465 36.45 37.21 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.56 f 0.032 0.046 0.81 1.17 g 0.070 bsc 1.778 bsc h 0.300 bsc 7.62 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.600 bsc 15.24 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.02 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications data sheet mc68HC908BD48 ? rev. 2.0 284 mechanical specifications motorola 22.4 44-pin plastic quad flat pack (qfp) figure 22-2. 44-pin qfp (case #824a) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. l 33 34 23 22 44 111 12 detail a ?d? ?a? a s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s b s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b v l ?b? ?c? seating plane m m e h g c ?h? datum plane detail c 0.10 (0.004) m ?h? datum plane t r k q w x detail c dim min max min max inches millimeters a 9.90 10.10 0.390 0.398 b 9.90 10.10 0.390 0.398 c 2.10 2.45 0.083 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.10 0.079 0.083 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ? 0.25 ? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 8.00 ref 0.315 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 12.95 13.45 0.510 0.530 t 0.13 ? 0.005 ? u 0 ?0 ? v 12.95 13.45 0.510 0.530 w 0.40 ? 0.016 ? x 1.6 ref 0.063 ref detail a b b ?a?, ?b?, ?d? s a?b m 0.20 (0.008) d s c f n section b?b j d base metal view rotated 90 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC908BD48 ? rev. 2.0 data sheet motorola ordering information 285 data sheet ? mc68HC908BD48 section 23. ordering information 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 23.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 23.2 introduction this section contains ordering numbers for the mc68HC908BD48. 23.3 mc order numbers table 23-1. mc order numbers mc order number operating temperature range package mc68HC908BD48ib 0 c to +85 c 42-pin sdip mc68HC908BD48ifb 0 c to +85 c 44-pin qfp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information data sheet mc68HC908BD48 ? rev. 2.0 286 ordering information motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc68HC908BD48/d rev. 2 9/2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in differen t applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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